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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES
3819
User's Manual
Group
keep safety first in your circuit designs ! q Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials q These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. q Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. q All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. q Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. q The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. q If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited. q Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Preface
This user's manual describes Mitsubishi's CMOS 8bit microcomputers 3819 Group. After reading this manual, the user should have a through knowledge of the functions and features of the 3819 Group, and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. For details of software, refer to the "740 Family Software MANUAL".
BEFORE USING THIS USER'S MANUAL
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development.
1. Organization
q CHAPTER 1 HARDWARE This chapter describes features of the microcomputer, operation of each peripheral function and electric characteristics. q CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. q CHAPTER 3 APPENDIX This chapter includes precautions for systems development using the microcomputer, a list of control registers, the masking confirmation (mask ROM version), and mark specifications which are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
(Note 2)
Bits
b7 b6 b5 b4 b3 b2 b1 b0 0
Bit attributes
(Note 1)
Contents immediately after reset release
CPU mode register (CPUM) [Address:3B 16] B 0 1 2 3 4 5 6 7 Stack page selection bit Name Processor mode bits
b1b0
Function
00: Single-chip mode 01: 10: Not available 11: 0 : 0 page 1 : 1 page
At reset
RW
0 0 0 0 0 1
T T
Nothing arranged for these bits. These are write disabled bits. When these bits are read out, the contents are "0". Fix this bit to "0". Main clock (XIN-XOUT) stop bit Internal system clock selection bit
0 : Operating 1 : Stopped 0 : XIN-XOUT selected 1 : XCIN-XCOUT selected
! !
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release 0******"0" at reset release 1******"1" at reset release Undefined******Undefined or reset release T ******Contents determined by option at reset release (D) Note Note 2. Bit attributes******The attributes of control register bits are classified into 3 bytes : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read ******Read enabled !******Read disabled W******Write ******Write enabled ! ******Write disabled T ******"0" write
Table of contents
Table of contents
CHAPTER 1. HARDWARE
Description ........................................................................................................................................ 2 Features ............................................................................................................................................. 2 Applications ...................................................................................................................................... 2 Pin configuration (Top view) ........................................................................................................ 2 Functional block diagram (Package:100P6S-A) ......................................................................... 3 Pin description ................................................................................................................................. 4 Part numbering ................................................................................................................................ 6 Group expansion ............................................................................................................................. 7 Functional description .................................................................................................................... 8 Central processing unit (CPU) ..................................................................................................... 8 CPU mode register ...................................................................................................................... 8 Memory .............................................................................................................................................. 9 Special function register (SFR) area ........................................................................................... 9 RAM ............................................................................................................................................. 9 ROM ............................................................................................................................................ 9 Interrupt vector area .................................................................................................................... 9 Zero page .................................................................................................................................... 9 Special page ................................................................................................................................ 9 I/O ports .......................................................................................................................................... 11 Direction registers ...................................................................................................................... 11 High-breakdown-voltage output ports ....................................................................................... 11 Interrupts ......................................................................................................................................... 17 Interrupt control ......................................................................................................................... 17 Interrupt operation ..................................................................................................................... 17 Notes on use ............................................................................................................................. 17 Timers .............................................................................................................................................. 19 Timer 1 and timer 2 ................................................................................................................... 19 Timer 3 and timer 4 ................................................................................................................... 19 Timer 5 and timer 6 ................................................................................................................... 19 Timer 6 PWM mode ................................................................................................................... 19 Serial I/O ......................................................................................................................................... 23 Serial I/O control registers (SIO1CON, SIO2CON, SIO3CON) 001916, 001D16, 001E16 ............ 23 Serial I/O automatic transfer control register (SIOAC) 001A16 .............................................................. 26 Serial I/O automatic transfer data pointer (SIODP) 001816 ..................................................................... 27 Serial I/O automatic transfer interval register (SIOAI) 001C16 ............................................................... 27 A-D converter ................................................................................................................................. 31 A-D conversion register (AD) 002D16 .............................................................................................................. 31 AD/DA control register (ADCON) 002C16 ...................................................................................................... 31 Comparison voltage generator .................................................................................................. 31 Channel selector ........................................................................................................................ 31 Comparator and control circuit .................................................................................................. 31 D-A converter ................................................................................................................................. 32 FLD controller ................................................................................................................................ 33 FLDC mode registers (FLDM1, FLDM2) 003616 , 003716 ....................................................................... 34 FLD data pointer and FLD data pointer reload register (FLDDP) 003816 .......................................... 36 Interrupt interval determination function .................................................................................. 41 Noise filter .................................................................................................................................. 41 Zero cross detection circuit ........................................................................................................ 44 Noise filter ...................................................................................................................................... 45
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RESET circuit ................................................................................................................................. 46 Clock generating circuit ............................................................................................................... 48 Frequency control ...................................................................................................................... 48 Oscillation control ...................................................................................................................... 48 Notes on programming ................................................................................................................ 51 Processor status register ........................................................................................................... 51 Interrupts ................................................................................................................................... 51 Decimal calculations .................................................................................................................. 51 Timers ........................................................................................................................................ 51 Multiplication and division instructions....................................................................................... 51 Ports .......................................................................................................................................... 51 Serial I/O .................................................................................................................................... 51 A-D converter ............................................................................................................................ 51 Instruction execution timing ....................................................................................................... 51 At the STP instruction release ................................................................................................... 51 Data required for mask orders .................................................................................................. 52 PROM programming method ....................................................................................................... 52 Absolute maximum ratings .......................................................................................................... 53 Recommended operating conditions ......................................................................................... 53 Electrical characteristics .............................................................................................................. 55 Zero cross detection input characteristics .............................................................................. 57 A-D converter characteristics ...................................................................................................... 57 D-A converter characteristics ...................................................................................................... 57 Timing requirements ..................................................................................................................... 58 Switching characteristics ............................................................................................................. 58 Timing diagram .............................................................................................................................. 59 Power source current characteristic examples ....................................................................... 60 Port standard characteristic examples ...................................................................................... 61 A-D conversion standard characteristics .................................................................................. 63 D-A conversion standard characteristics .................................................................................. 64 Functional description supplement ............................................................................................ 65 Interrupt ..................................................................................................................................... 65 Timing after interrupt ................................................................................................................. 66 A-D converter ............................................................................................................................ 67
CHAPTER 2. APPLICATION
2.1 I/O port ..................................................................................................................................... 70 2.1.1 Related registers .............................................................................................................. 70 2.1.2 Handling of unused pins ................................................................................................... 71 2.2 Timer ......................................................................................................................................... 72 2.2.1 Related registers .............................................................................................................. 72 2.2.2 Timer application examples .............................................................................................. 77 2.3 Serial I/O .................................................................................................................................. 86 2.3.1 Related registers .............................................................................................................. 86 2.3.2 Serial I/O connection examples ........................................................................................ 91 2.3.3 Setting of serial I/O mode ................................................................................................. 93 2.3.4 Serial I/O application examples ........................................................................................ 94 2.4 A-D conversion ..................................................................................................................... 105 2.4.1 Related registers ............................................................................................................ 105 2.4.2 A-D conversion application example .............................................................................. 107
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2.5 FLD controller ....................................................................................................................... 109 2.5.1 Related registers ............................................................................................................ 109 2.5.2 FLD controller application examples .............................................................................. 115 2.6 Interrupt interval determination function ......................................................................... 139 2.6.1 Related registers ............................................................................................................ 139 2.6.2 Interrupt interval determination function ......................................................................... 142 2.7 Zero cross detection circuit ............................................................................................... 147 2.7.1 Related registers ............................................................................................................ 147 2.7.2 Connection example of Zero cross detection circuit ....................................................... 149 2.7.3 Zero cross detection circuit application example 1 ......................................................... 150 2.7.4 Zero cross detection circuit application example 2 ......................................................... 152 2.8 Reset ....................................................................................................................................... 154 2.8.1 Connection example of reset IC ..................................................................................... 154 2.9 Clock generating circuit ...................................................................................................... 155 2.9.1 Related registers ........................................................................................................... 155 2.9.2 Clock generating circuit application examples .............................................................. 160
CHAPTER 3. APPENDIX
3.1 Notes on use ........................................................................................................................ 170 3.1.1 Notes on interrupts ......................................................................................................... 170 3.1.2 Notes on the FLD controller and the serial I/O automatic transfer function .................... 170 3.1.3 Notes on the A-D converter ............................................................................................ 170 3.1.4 Notes on the RESET pin ................................................................................................ 171 3.1.5 Notes on input and output pins ....................................................................................... 171 3.1.6 Notes on clock synchronous serial I/O ........................................................................... 172 3.1.7 Notes on built-in PROM .................................................................................................. 173 3.2 Countermeasures against noise ........................................................................................ 174 3.2.1 Shortest wiring length ..................................................................................................... 174 3.2.2 Connection of a bypass capacitor across the VSS line and the VCC line ........................ 175 3.2.3 Wiring to analog input pins ............................................................................................. 176 3.2.4 Oscillator concerns ......................................................................................................... 176 3.2.5 Setup for I/O ports .......................................................................................................... 177 3.2.6 Providing of watchdog timer function by software .......................................................... 177 3.3 Control registers ................................................................................................................... 179 3.4 Mask ROM ordering method .............................................................................................. 196 3.5 Mark specification form ...................................................................................................... 198 3.6 Package outline .................................................................................................................... 199 3.7 Memory map .......................................................................................................................... 200 3.8 Pin configuration .................................................................................................................. 201
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List of figures
CHAPTER 1. HARDWARE
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 1 Structure of CPU mode register ................................................................................................. 8 2 Memory map .................................................................................................................................. 9 3 Memory map of special function register (SFR) .................................................................... 10 4 Port block diagram (1) ............................................................................................................... 13 5 Port block diagram (2) ............................................................................................................... 14 6 Port block diagram (3) ............................................................................................................... 15 7 Port block diagram (4) ............................................................................................................... 16 8 Interrupt control ........................................................................................................................... 18 9 Structure of interrupt related registers ..................................................................................... 18 10 Timer block diagram ................................................................................................................. 20 11 Structure of timer related registers ........................................................................................ 21 12 Timing in timer 6 PWM mode ................................................................................................. 22 13 Serial I/O block diagram .......................................................................................................... 24 14 Structure of serial I/O control registers ................................................................................. 25 15 Serial I/O timing in the serial I/O ordinary mode (for LSB first) ....................................... 26 16 Structure of serial I/O automatic transfer control register .................................................. 26 17 Bit allocation of serial I/O automatic transfer RAM ............................................................. 27 18 Serial I/O automatic transfer interval timing ......................................................................... 27 19 Serial I/O1 register transfer operation in full duplex mode ................................................ 28 20 Timing chart during serial I/O automatic transfer (internal clock selected, SRDY used) ..................................................................................... 29 21 Timing chart during serial I/O automatic transfer (internal clock selected, SCLK11 and SCLK12 used) .............................................................. 29 22 Timing during serial I/O automatic transfer (external clock selected) .............................. 30 23 Structure of A-D control register ............................................................................................ 31 24 A-D converter block diagram .................................................................................................. 32 25 D-A converter block diagram .................................................................................................. 32 26 Equivalent connection circuit of D-A converter .................................................................... 32 27 FLD control circuit block diagram .......................................................................................... 33 28 Structure of FLDC mode register 1 ....................................................................................... 34 29 Structure of FLDC mode register 2 ....................................................................................... 34 30 Segment/digit setting example ................................................................................................ 35 31 FLD automatic display RAM and bit allocation .................................................................... 37 32 Example of using the FLD automatic display RAM (1) ....................................................... 38 33 Example of using the FLD automatic display RAM (2) (continued) .................................. 39 34 FLDC timing ............................................................................................................................... 40 35 Block diagram of interrupt interval determination circuit ..................................................... 41 36 Structure of interrupt interval determination control register .............................................. 42 37 Interrupt interval determination operation example (at rising edge active) ...................... 42 38 Interrupt interval determination operation example (at both-sided edge active) ............. 43 39 External circuit example for zero cross detection ................................................................ 44 40 Structure of zero cross detection control register................................................................ 44 41 Block diagram of zero cross detection circuit ...................................................................... 44 42 Noise filter circuit diagram ...................................................................................................... 45
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Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Timing of noise filter circuit..................................................................................................... 45 Example of reset circuit ........................................................................................................... 46 Reset sequence ........................................................................................................................ 46 Internal state at reset ............................................................................................................... 47 Ceramic resonator external circuit ......................................................................................... 48 External clock input circuit ...................................................................................................... 48 Clock generating circuit block diagram ................................................................................. 49 State transition of system clock ............................................................................................. 50 Programming and testing of One Time PROM version ...................................................... 52 Zero cross detection input characteristics ............................................................................ 57 Circuit for measuring output switching characteristics ........................................................ 58 Power source current characteristic example ....................................................................... 60 Power source current characteristic example (in wait mode) ............................................ 60 Standard characteristic example of High-breakdown-voltage P-channel open-drain output port .................. 61 Standard characteristic example of CMOS output port at P-channel drive ..................... 61 Standard characteristic example of CMOS output port at N-channel drive ..................... 62 A-D conversion standard characteristics ............................................................................... 63 D-A conversion standard characteristics ............................................................................... 64 Timing chart after an interrupt occurs ................................................................................... 66 Time up to execution of the interrupt processing routine .................................................. 66 A-D conversion equivalent circuit ........................................................................................... 68 A-D conversion timing chart .................................................................................................... 68
CHAPTER 2. APPLICATION
Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B) ............................................ 70 2.1.2 Structure of Port P2 direction register .............................................................................. 70 2.1.3 Structure of Port Pi direction register (i = 4, 5, 6, 7, 8, A, B) ..................................... 71 2.2.1 Structure of Timer i (i = 1, 3, 4, 5, 6) .............................................................................. 72 2.2.2 Structure of Timer 2 ............................................................................................................. 72 2.2.3 Structure of Timer 6 PWM register ................................................................................... 73 2.2.4 Structure of Timer 12 mode register ................................................................................. 73 2.2.5 Structure of Timer 34 mode register ................................................................................. 74 2.2.6 Structure of Timer 56 mode register ................................................................................. 74 2.2.7 Structure of Interrupt request register 1 ........................................................................... 75 2.2.8 Structure of Interrupt request register 2 ........................................................................... 75 2.2.9 Structure of Interrupt control register 1 ............................................................................ 76 2.2.10 Structure of Interrupt control register 2 .......................................................................... 76 2.2.11 Connection of timers and setting of division ratios [Clock function] .......................... 78 2.2.12 Setting of related registers (1) [Clock function] ............................................................. 78 2.2.13 Setting of related registers (2) [Clock function] ............................................................. 79 2.2.14 Control procedure [Clock function] .................................................................................. 80 2.2.15 Example of a peripheral circuit ........................................................................................ 81 2.2.16 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output].... 81 2.2.17 Setting of related registers [Piezoelectric buzzer output] ............................................. 82 2.2.18 Control procedure [Piezoelectric buzzer output] ............................................................ 82 2.2.19 A method for judging if Video synchronization signal exists ....................................... 83 2.2.20 Setting of related registers [Measurement of frequency] ............................................. 84 2.2.21 Control procedure [Measurement of frequency] ............................................................. 85 2.3.1 Structure of Serial I/O automatic transfer data pointer .................................................. 86 2.3.2 Structure of Serial I/O 1 control register .......................................................................... 86
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Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.3 Structure of Serial I/O automatic transfer control register ............................................. 87 2.3.4 Structure of Serial I/O 1 register ....................................................................................... 87 2.3.5 Structure of Serial I/O automatic transfer interval register ............................................ 88 2.3.6 Structure of Serial I/O 2 control register .......................................................................... 88 2.3.7 Structure of Serial I/O 3 control register .......................................................................... 89 2.3.8 Structure of Interrupt request register 1 ........................................................................... 89 2.3.9 Structure of Interrupt control register 1 ............................................................................ 90 2.3.10 Serial I/O connection examples (1) ................................................................................. 91 2.3.11 Serial I/O connection examples (2) ................................................................................. 92 2.3.12 Setting of Serial I/O mode ................................................................................................ 93 2.3.13 Connection diagram [Output of serial data] ................................................................... 94 2.3.14 Timing chart [Output of serial data] ................................................................................ 94 2.3.15 Setting of related registers [Output of serial data] ........................................................ 95 2.3.16 Setting of transmission data [Output of serial data] ..................................................... 95 2.3.17 Control procedure [Output of serial data] ....................................................................... 96 2.3.18 Connection diagram [Data transmission or reception using automatic transfer] ....... 97 2.3.19 Timing chart [Data transmission or reception using automatic transfer] .................... 97 2.3.20 Setting of related registers [Data transmission or reception using automatic transfer] ................ 98 2.3.21 Setting of transmission data [Data transmission or reception using automatic transfer] ............. 99 2.3.22 Control procedure [Data transmission or reception using automatic transfer] ............................... 100 2.3.23 Connection diagram [Cyclic transmission or reception of block data between microcomputers] ........... 101 2.3.24 Timing chart [Cyclic transmission or reception of block data between microcomputers] ............... 102 2.3.25 Setting of related registers [Cyclic transmission or reception of block data between microcomputers] ........... 102 2.3.26 Control in the master unit .............................................................................................. 103 2.3.27 Control in the slave unit ................................................................................................. 104 2.4.1 Structure of AD/DA control register ................................................................................ 105 2.4.2 Structure of A-D conversion register .............................................................................. 105 2.4.3 Structure of Interrupt request register 2 ........................................................................ 106 2.4.4 Structure of Interrupt control register 2 ......................................................................... 106 2.4.5 Connection diagram [Conversion of Analog input voltage] ......................................... 107 2.4.6 Setting of related registers [Conversion of Analog input voltage] ............................. 107 2.4.7 Control procedure [Conversion of Analog input voltage] ............................................. 108 2.5.1 Structure of Port P0 segment/digit switch register ....................................................... 109 2.5.2 Structure of Port P2 digit/port switch register ............................................................... 109 2.5.3 Structure of Port P8 segment/port switch register ....................................................... 110 2.5.4 Structure of Port PA segment/port switch register ....................................................... 110 2.5.5 Structure of FLDC mode register 1 ................................................................................ 111 2.5.6 Structure of FLDC mode register 2 ................................................................................ 112 2.5.7 Structure of FLD data pointer ......................................................................................... 113 2.5.8 Structure of FLD data pointer reload register ............................................................... 113 2.5.9 Structure of Interrupt request register 2 ........................................................................ 114 2.5.10 Structure of Interrupt control register 2 ....................................................................... 114 2.5.11 Connection diagram [FLD automatic display and Key-scan using segment pin] ... 115 2.5.12 Timing chart [FLD automatic display and Key-scan using segment pin] .............. 115 2.5.13 Enlarged view of SEG24 to SEG31 during Tscan ....................................................... 116 2.5.14 Setting of related registers (1) [FLD automatic display and Key-scan using segment pin] .... 116 2.5.15 Setting of related registers (2) [FLD automatic display and Key-scan using segment pin] .... 117 2.5.16 Example of FLD digit allocation [FLD automatic display and Key-scan using segment pin] . 119 2.5.17 Control procedure [FLD automatic display and Key-scan using segment pin] ...... 120
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Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.5.18 Control procedure of Segment key-scan ..................................................................... 121 2.5.19 Connection diagram [FLD automatic display and Key-scan using digit pin] .......... 122 2.5.20 Timing chart [FLD automatic display and Key-scan using digit pin] ...................... 122 2.5.21 Setting of related registers (1) [FLD automatic display and Key-scan using digit pin] ........... 123 2.5.22 Setting of related registers (2) [FLD automatic display and Key-scan using digit pin] ........... 124 2.5.23 Example of FLD digit allocation [FLD automatic display and Key-scan using digit pin] ......... 126 2.5.24 Control procedure [FLD automatic display and Key-scan using digit pin] .............. 127 2.5.25 Control procedure of Digit key-scan ............................................................................. 128 2.5.26 Connection diagram [FLD display by software] .......................................................... 129 2.5.27 Timing chart [FLD display by software] ....................................................................... 129 2.5.28 Enlarged view of Key-scan of ports P30 to P37 ......................................................... 130 2.5.29 Setting of related registers [FLD display by software] .............................................. 130 2.5.30 Example of FLD digit allocation [FLD display by software] ...................................... 131 2.5.31 Control procedure [FLD display by software] .............................................................. 132 2.5.32 Connection diagram [5 ! 7 dot display] ...................................................................... 133 2.5.33 Timing chart [5 ! 7 dot display] ................................................................................... 133 2.5.34 Setting of related registers (1) [5 ! 7 dot display] .................................................... 134 2.5.35 Setting of related registers (2) [5 ! 7 dot display] .................................................... 135 2.5.36 Example of FLD digit allocation and segment arrangment ....................................... 137 2.5.37 Setting example of display data (in case of using DIG11 pin) ................................. 137 2.5.38 Control procedure [5 ! 7 dot display] ......................................................................... 138 2.6.1 Structure of Interrupt interval determination register ................................................... 139 2.6.2 Structure of Interrupt interval determination control register ...................................... 139 2.6.3 Structure of Interrupt edge selection register ............................................................... 140 2.6.4 Structure of Interrupt request register 1 ........................................................................ 140 2.6.5 Structure of Interrupt control register 1 ......................................................................... 141 2.6.6 Connection diagram [Reception of remote-control signal] ........................................... 142 2.6.7 Function block diagram [Reception of remote-control signal] ..................................... 142 2.6.8 Timing chart of data determination ................................................................................. 143 2.6.9 Setting of related registers [Reception of remote-control signal] ............................... 144 2.6.10 Control procedure (1) [Reception of remote-control signal] ...................................... 145 2.6.11 Control procedure (2) [Reception of remote-control signal] (Timer 2 interrupt) ..... 146 2.7.1 Structure of Zero cross detection control register ........................................................ 147 2.7.2 Structure of Interrupt edge selection register ............................................................... 147 2.7.3 Structure of Interrupt request register 1 ........................................................................ 148 2.7.4 Structure of Interrupt control register 1 ......................................................................... 148 2.7.5 Connection example of Zero cross detection circuit .................................................... 149 2.7.6 Setting of related registers [Clock count using ZCR interrupt (without using a noise filter)] ................................ 150 2.7.7 Control procedure [Clock count using ZCR interrupt (without using a noise filter)] ....................... 151 2.7.8 Setting of related registers [Clock count using ZCR interrupt (using a noise filter)]................... 152 2.7.9 Control procedure [Clock count using ZCR interrupt (using a noise filter)] ..................................... 153 2.8.1 Example of Poweron reset circuit ................................................................................... 154 2.8.2 RAM back-up system ........................................................................................................ 154 2.9.1 Structure of Timer i ........................................................................................................... 155 2.9.2 Structure of Timer 2 .......................................................................................................... 155 2.9.3 Structure of Timer 12 mode register .............................................................................. 156 2.9.4 Structure of Timer 34 mode register .............................................................................. 156 2.9.5 Structure of CPU mode register ...................................................................................... 157 2.9.6 Structure of Interrupt request register 1 ........................................................................ 157 2.9.7 Structure of Interrupt request register 2 ........................................................................ 158
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Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.9.8 Structure of Interrupt control register 1 ......................................................................... 158 2.9.9 Structure of Interrupt control register 2 ......................................................................... 159 2.9.10 Connection diagram [Status transition upon a power failure] ................................... 160 2.9.11 Status transition diagram upon a power failure .......................................................... 160 2.9.12 Setting of related registers [Status transition upon a power failure] ....................... 161 2.9.13 Control procedure [Status transition upon a power failure] ...................................... 162 2.9.14 Connection diagram [Counting without clock errors during a power failure] .......... 163 2.9.15 Timing chart of counting without clock errors during a power failure ..................... 163 2.9.16 Structure of a clock counter .......................................................................................... 164 2.9.17 Setting of related registers (1) [Counting without clock errors during a power failure] ........... 165 2.9.18 Setting of related registers (2) [Counting without clock errors during a power failure] ........... 166 2.9.19 Control procedure (1) [Counting without clock errors during a power failure] ....... 167 2.9.20 Control procedure (2) [Counting without clock errors during a power failure] ....... 168 3.1.1 Structure of interrupt control register 2 .......................................................................... 170 3.2.1 Wiring for the RESET pin ................................................................................................ 174 3.2.2 Wiring for clock I/O pins .................................................................................................. 175 3.2.3 Wiring for the VPP pin of the One Time PROM and the EPROM version ............... 175 3.2.4 Bypass capacitor across the VSS line and the VCC line ............................................. 175 3.2.5 Analog signal line and a resistor and a capacitor ....................................................... 176 3.2.6 Wiring for a large current signal line ............................................................................. 176 3.2.7 Wiring to a signal line where potential levels change frequently .............................. 176 3.2.8 Setup for I/O ports ............................................................................................................ 177 3.2.9 Watchdog timer by software ............................................................................................ 177 3.3.1 Structure of Port Pi direction register ............................................................................ 179 3.3.2 Structure of Port P2 direction register ........................................................................... 179 3.3.3 Structure of Serial I/O automatic transfer data pointer ............................................... 180 3.3.4 Structure of Serial I/O 1 control register ....................................................................... 180 3.3.5 Structure of Serial I/O automatic transfer control register .......................................... 181 3.3.6 Structure of Serial I/O automatic transfer interval register ......................................... 181 3.3.7 Structure of Serial I/O 2 control register ....................................................................... 182 3.3.8 Structure of Serial I/O 3 control register ....................................................................... 182 3.3.9 Structure of Timer 12 mode register .............................................................................. 183 3.3.10 Structure of Timer 34 mode register ............................................................................ 183 3.3.11 Structure of Timer 56 mode register ............................................................................ 184 3.3.12 Structure of AD/DA control register .............................................................................. 185 3.3.13 Structure of Interrupt interval determination register ................................................. 186 3.3.14 Structure of Interrupt interval determination control register .................................... 186 3.3.15 Structure of Port P0 segment/digit switch register ..................................................... 187 3.3.16 Structure of Port P2 digit/port switch register ............................................................. 187 3.3.17 Structure of Port P8 segment/port switch register ..................................................... 188 3.3.18 Structure of Port PA segment/port switch register ..................................................... 188 3.3.19 Structure of FLDC mode register 1 .............................................................................. 189 3.3.20 Structure of FLDC mode register 2 .............................................................................. 190 3.3.21 Structure of FLD data pointer ....................................................................................... 191 3.3.22 Structure of FLD data pointer reload register ............................................................. 191 3.3.23 Structure of Zero cross detection control register ...................................................... 192 3.3.24 Structure of Interrupt edge selection register ............................................................. 192 3.3.25 Structure of CPU mode register.................................................................................... 193 3.3.26 Structure of Interrupt request register 1 ...................................................................... 193 3.3.27 Structure of Interrupt request register 2 ...................................................................... 194 3.3.28 Structure of Interrupt control register 1 ....................................................................... 194 3.3.29 Structure of Interrupt control register 2 ....................................................................... 195
3819 Group USER'S MANUAL
viii
Table of contents
List of tables
CHAPTER 1. HARDWARE
Table 1. Interrupt vector addresses and priority ......................................................................................... 17 Table 2. SCLK11 and SCLK12 selection ........................................................................................................ 29 Table 3. P67/SRDY1/CS selection ................................................................................................................ 30 Table 4. Pins in FLD automatic display mode ............................................................................................ 35 Table 5. Interrupt sources, vector addresses and interrupt priority ............................................................ 65 Table 6. Change of A-D conversion register during A-D conversion .......................................................... 67
CHAPTER 2. APPLICATION
Table 2.1.1 Handling of unused pins .......................................................................................................... 71 Table 2.5.1 FLD automatic display RAM map [FLD automatic display and Key-scan segment pin] ........ 118 Table 2.5.2 FLD automatic display RAM map example [FLD automatic display and Key-scan segment pin] ......... 119 Table 2.5.3 FLD automatic display RAM map [FLD automatic display and Key-scan digit pin] ............. 125 Table 2.5.4 FLD automatic display RAM map example [FLD automatic display and Key-scan digit pin] ............... 126 Table 2.5.5 FLD automatic display RAM map example [FLD display by software] (Automatic display is not performed because of not using FLD controller) ........................... 131 Table 2.5.6 FLD automatic display RAM map [5 ! 7 dot display] ............................................................ 136
CHAPTER 3. APPENDIX
Table 3.1.1 Programming adapter ............................................................................................................ 173 Table 3.1.2 Setting of programming adapter switch ................................................................................ 173 Table 3.1.3 Setting of PROM programmer address ................................................................................. 173
ix
3819 Group USER'S MANUAL
CHAPTER 1 HARDWARE
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3819 group is a 8-bit microcomputer based on the 740 family core technology. The 3819 group has a flourescent display automatic display circuit and an 16-channel 8-bit A-D converter as additional functions. The various microcomputers in the 3819 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3819 group, refer to the section on group expansion.
FEATURES
qBasic machine-language instructions ...................................... 71 qThe minimum instruction execution time ......................... 0.48 s (at 8.4 MHz oscillation frequency) qMemory size ................................................................................. ROM ............................................. 4K to 60 K bytes RAM ........................................... 192 to 2048 bytes qProgrammable input/output ports ............................................ 54 qHigh-breakdown-voltage output ports ...................................... 52 qInterrupts ................................................. 20 sources, 16 vectors qTimers ............................................................................. 8-bit ! 6 qSerial I/O (Serial I/O1 has an automatic transfer function) ...................................................... 8-bit ! 3(clock-synchronized) qPWM output circuit ............... 8-bit ! 1(also functions as timer 6) qA-D converter ............................................... 8-bit ! 16 channels
qD-A converter ................................................. 8-bit ! 1 channels qZero cross detection input ............................................ 1 channel qFluorescent display function Segments ........................................................................ 16 to 42 Digits .................................................................................. 6 to 16 q2 Clock generating circuit Clock (XIN-XOUT) ................................. Internal feedback resistor Sub-clock (XCIN-XCOUT) ......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) qPower source voltage In high-speed mode .................................................. 4.0 to 5.5 V (at 8.4 MHz oscillation frequency and high-speed selected) In middle-speed mode ............................................... 2.8 to 5.5 V (at 8.4 MHz oscillation frequency) In low-speed mode .................................................... 2.8 to 5.5 V (at 32 kHz oscillation frequency) qPower dissipation In high-speed mode .......................................................... 35 mW (at 8.4 MHz oscillation frequency) In low-speed mode ............................................................ 60 W (at 3 V power source voltage and 32 kHz oscillation frequency ) qOperating temperature range .................................... -10 to 85C
APPLICATION
Musical Instruments, household appliance, etc.
PIN CONFIGURATION (TOP VIEW)
P90/SEG16 P91/SEG17 P92/SEG18 P93/SEG19 P94/SEG20 P95/SEG21 P96/SEG22 P97/SEG23 P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 P00/SEG32/DIG0 P01/SEG33/DIG1 P02/SEG34/DIG2 P03/SEG35/DIG3 P04/SEG36/DIG4 P05/SEG37/DIG5 P06/SEG38/DIG6 P07/SEG39/DIG7 P10/SEG40/DIG8 P11/SEG41/DIG9 P12/DIG10 P13/DIG11 P14/DIG12 P15/DIG13
75 74 60 77 76 61 68 78 80 79 69 62 59 58 57 56 55 54 53 72 73 63 70 71
P87/SEG15 P86/SEG14 P85/SEG13 P84/SEG12 P83/SEG11 P82/SEG10 P81/SEG9 P80/SEG8 PA7/SEG7 PA6/SEG6 VCC PA5/SEG5 PA4/SEG4 PA3/SEG3 PA2/SEG2 PA1/SEG1 PA0/SEG0 VEE AVSS VREF
67
66
65
64
52
51
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43
M38197MA-XXXFP
42 41 40 39 38 37 36 35 34 33 32 31
P16/DIG14 P17/DIG15 P20/DIG16 P21/DIG17 P22/DIG18 P23/DIG19 P24 P25 P26 P27 VSS XOUT XIN PB0/XCOUT PB1/XCIN RESET P40/INT0 P41 P42/INT2 P43/INT3
21
20
12
19
22
23
24
25
26
27
18
17
11
10
2
P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 PB3 PB2/DA P57/SRDY3/AN15 P56/SCLK3/AN14 P55/SOUT3/AN13 P54/SIN3/AN12 P53/SRDY2/AN11 P52/SCLK2/AN10 P51/SOUT2/AN9 P50/SIN2/AN8 P67/SRDY1/CS/SCLK12 P66/SCLK11 P65/SOUT1 P64/SIN1 P63/CNTR1 P62/CNTR0 P61/PWM P60 P47/T3OUT P46/T1OUT P45/INT1/ZCR P44/INT4
Package type : 100P6S-A 100-pin plastic-molded QFP
13
14
15
16
28
29
30
1
2
3
4
5
6
7
8
9
FUNCTIONAL BLOCK DIAGRAM (Package : 100P6S-A)
Output port P0 VEE
92 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
Clock input XIN
Reset input RESET (5 V) VCC
91 40
Clock output XOUT
(0 V) VSS Output port P1 Output port P2(4) I/O port P2(4)
35
38
39
Data bus P0 (8) P1 (8) P2 (8)
Clock generating circuit ROM RAM A X Y S T3OUT PWM CNTR0 CNTR1
FLD automatic display RAM 96 bytes
CPU
Timer 1 (8) Timer 2 (8) Timer 3 (8) Timer 4 (8) Timer 5 (8) Timer 6 (8)
T1OUT
FLD automatic display controller
XCIN XCOUT Sub-clock Sub-clock input output
PCH
PCL PS
SI/O automatic transfer controller SI/O automatic transfer RAM 32 bytes
9 10 36 37 81 82 83 84 85 86 87 88
89 90 92 93 94 95 96 97 73 74 75 76 77 78 79 80
12345678
99100
19 20 21 22 23 24 25 26
11 12 13 14 15 16 17 18
27 28 29 30 31 32 33 34
I/O port PB I/O port P8
I/O port PA
Output port P9
I/O port P7
AVSS VREF
I/O port P6
I/O port P5
INT0
PB (4) P8 (8) P7 (8)
PA (8)
P9 (8)
P6 (8)
P5 (8)
Zero cross detection circuit
P4 (8)
Interrupt interval determination circuit
16
INT3, INT4
XCIN
INT1/ZCR
D-A converter (8) A-D converter (8)
S I/O1(8)
S I/O2(8)
S I/O3(8)
INT2
XCOUT
Local data bus
P3 (8)
65 66 67 68 69 70 71 72
I/O port P4(6) Input port P4(2)
Output port P3
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3819 Group
3
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin VCC, VSS VEE VREF AVSS RESET XIN Name Power source Pull-down Power source Analog reference voltage Analog power source Reset input Clock input Function *Apply voltage of 4.0 to 5.5 V to VCC, and 0 V to VSS. *Applies voltage supplied to pull-down resistors of ports P0, P1, P20-P23, P3, and P9. *Reference voltage input pin for A-D converter and D-A converter *GND input pin for A-D converter and D-A converter *Connect AVSS to VSS. *Reset input pin for active "L" *Input and output pins for the main clock generating circuit *Feedback resistor is built in between XIN pin and XOUT pin. *Connect a ceramic resonator or a quartz-crystal oscillator between the XIN pin and XOUT pin to set oscillation frequency. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *This clock is used as the oscillating source of system clock. *8-bit output port *This port builds in pull-down resistor between port P0 and the VEE pin. *At reset this port is set to VEE level. *The high-breakdown-voltage P-channel open-drain *8-bit output port with the same function as port P0 *4-bit output port with the same function as port P0 Function except a port function
XOUT
Clock output
P00/SEG32/ DIG0-P07/ SEG39/DIG7
Output port P0
FLD automatic display pins
P10/SEG40/ DIG8-P17/ DIG15 P20/DIG16- P23/DIG19
Output port P1
FLD automatic display pins
Output port P2
FLD automatic display pins
P24-P27
I/O port P2
*4-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *At reset this port is set to input mode. *TTL input level *CMOS 3-state output *8-bit output port with the same function as port P0 *2-bit input port *CMOS compatible input level FLD automatic display pins
P30/SEG24- P37/SEG31 P40/INT0, P45/INT1/ ZCR P42/INT2- P44/INT4 P41 P46/T1OUT, P47/T3OUT
Output port P3
Input port P4
External interrupt input pins A zero cross detection circuit input pin (P45)
I/O port P4
*6-bit CMOS I/O port with the same function as ports P24-P27 *CMOS compatible input level *CMOS 3-state output
Timer output pins
4
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (Continued)
Pin P50/SIN2/AN8, P51/SOUT2/AN9, P52/SCLK2/AN10, P53/SRDY2/AN11 P54/SIN3/AN12, P55/SOUT3/AN13, P56/SCLK3/AN14, P57/SRDY3/AN15 P60 P61/PWM P62/CNTR0, P63/CNTR1 P64/SIN1, P65/SOUT1, P66/SCLK11, P67/SRDY1/CS/ SCLK12 P70/AN0- P77/AN7 Name Function Function except a port function Serial I/O2 function pins A-D conversion input pins
I/O port P5
*8-bit CMOS I/O port with the same function as ports P24-P27 *CMOS compatible input level *CMOS 3-state output
Serial I/O3 function pins A-D conversion input pins
PWM output pin (Timer output pin) I/O port P6 *8-bit CMOS I/O port with the same function as ports P24-P47 *CMOS compatible input level *CMOS 3-state output Timer input pins
Serial I/O1 function pins
I/O port P7
*8-bit CMOS I/O port with the same function as ports P24-P27 *CMOS compatible input level *CMOS 3-state output *8-bit I/O port with the same function as ports P24-P27 *CMOS compatible input level *The high-breakdown-voltage P-channel open-drain *8-bit output port with the same function as port P0 *8-bit I/O port with the same function as ports P24-P27 *CMOS compatible input level *The high-breakdown voltage P-channel opendrain *4-bit CMOS I/O port with the same function as ports P24-P27 *CMOS compatible input level *CMOS 3-state output
A-D conversion input pins
P80/SEG8- P87/SEG15
I/O port P8
P90/SEG16- P97/SEG23
Output port P9
FLD automatic display pins
PA0/SEG0- PA7/SEG7
I/O port PA
PB0/XCOUT, PB1/XCIN PB2/DA PB3
I/O port PB
I/O pins for sub-clock generating circuit (connect a ceramic resonator or a quarts-crystal oscillator) D-A conversion output pin
5
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M3819
7
M
A
XXX FP Package type FP : 100P6S-A package FS : 100D0 package ROM number Omitted in some types. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes
6
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Mitsubishi plans to expand the 3819 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions ROM/PROM capacity .................................. 40 K to 60 K bytes RAM capacity .............................................. 1024 to 2048 bytes
(2) Packages 100P6S-A ........................... 0.65 mm-pitch plastic molded QFP 100D0 ........................... Ceramic LCC(built-in EPROM version)
Memory Expansion Plan
Under development 60K 56K 52K 48K 44K 40K 36K 32K 28K 24K 20K 16K 12K 8K 4K 256 512 768 1,024 RAM size (bytes) 1,536 2,048 Mass product M38197MA Mass product M38198MC/EC ROM size (bytes) M38199MF/EF
Products under development : the development schedule and specifications may be revised without notice.
Currently supported products are listed below. Product M38197MA-XXXFP M38197MA-XXXKP M38198MC-XXXKP M38199MF-XXXKP M38198MC-XXXFP M38198EC-XXXFP M38198ECFP M38198ECFS M38199MF-XXXFP M38199EF-XXXFP M38199EFFP M38199EFFS (P) ROM size (bytes) ROM size for User in ( ) 40960 (40830) RAM size (bytes) Package 100P6S-A 1024 100P6P-E Remarks
As of May 1996
49152 (49022)
1536
100P6S-A 100D0
61440 (61310)
2048
100P6S-A 100D0
Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version
7
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION Central Processing Unit (CPU)
The 3819 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST, SLW instruction cannot be used. The MUL, DIV, WIT and STP instruction can be used.
CPU Mode Register
The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit.
b7
b0 CPU mode register (CPUM (CM) : address 003B 16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1: 1 0 : Not available 1 1: Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area XCOUT drivability selection bit 0 : Low drive 1 : High drive Port XC switch bit 0 : I/O port function 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : XIN-XOUT selected (middle/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
Fig. 1 Structure of CPU mode register
8
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory Special function register (SFR) area
The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
Special page ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the reset is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area RAM capacity (bytes) 192 256 384 512 640 768 896 1024 1536 2048 Address XXXX16 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16
000016 SFR area 004016 010016 RAM Zero page
XXXX16 Reserved area 044016 Not used 0F0016 0F1F16
RAM area for serial I/O automatic transfer
Not used ROM area ROM capacity (bytes) 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 Address YYYY16 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 Address ZZZZ16 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 FFFE16 FFFF16 Reserved ROM area FFDC16 Interrupt vector area Special page ROM FF0016 ZZZZ16 0F8016 0FDF16 YYYY16 Reserved ROM area (common ROM area,128 bytes)
RAM area for FLD automatic display
Not used
Fig. 2 Memory map
9
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16
Port P0 (P0) Port P1 (P1) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Port PA (PA) Port PA direction register (PAD) Port PB (PB) Port PB direction register (PBD)
Serial I/O automatic transfer data pointer (SIODP)
Serial I/O1 control register (SIO1CON)
Serial I/O automatic transfer control register (SIOAC)
Serial I/O1 register (SIO1)
Serial I/O automatic transfer interval register (SIOAI)
Serial I/O2 control register (SIO2CON) Serial I/O3 control register (SIO3CON) Serial I/O2 register (SIO2)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 5 (T5) Timer 6 (T6) Serial I/O3 register (SIO3) Timer 6 PWM register (T6PWM) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer 56 mode register (T56M) D-A conversion register (DA) AD-DA control register (ADCON) A-D conversion register (AD)
Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
Port P0 segment/digit switch register (P0SDR) Port P2 digit/port switch register (P2DPR) Port P8 segment/port switch register (P8SPR) Port PA segment/port switch register (PASPR) FLDC mode register 1 (FLDM1) FLDC mode register 2 (FLDM2) FLD data pointer (FLDDP) Zero cross detection control register (ZCRCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Fig. 3 Memory map of special function register (SFR)
10
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS Direction Registers
The 3819 group has 54 programmable I/O pins arranged in 8 I/O ports (ports P24-P27, P41-P44, P46, P47, P5-P8, PA, and PB). The I/O ports have direction registers which determine the input/ output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input or output. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that bit, that pin becomes an output pin. If data is read from a pin which is set for output, the value of the port latch is read, not the value of the pin itself. A pin which is set for input the value of the pin itself is read because the pin is in floating state. If a pin set for input is written to, only the port latch is written to and the pin remains floating.
High-Breakdown-Voltage Output Ports
The 3819 group microprocessors have 7 ports with high-breakdown-voltage pins (ports P0, P1, P20-P23, P3, P8, P9, PA). The high-breakdown-voltage ports have P-channel open-drain output with VCC -40 V of breakdown voltage. Each pin in ports P0, P1, P20-P23, P3, and P9 has an internal pull-down resistor connected to VEE. Ports P8 and PA have no internal pull-down resistors, so that connect an external resistor to each port. At reset, the P-channel output transistor of each port latch is turned off, so it becomes VEE level ("L") by the pull-down resistor. Writing "1" (weak drivability) to bit 7 of the FLDC mode register 1 (address 003616) shows the rising transition of the output transistors for reducing transient noise. At reset, bit 7 of the FLDC mode register 1 is set to "0" (strong drivability).
Pin P00/SEG32/ DIG0- P07/SEG39/ DIG7
Name
Input/Output
I/O Format High-breakdownvoltage P-channel open-drain output with pull-down resistor High-breakdownvoltage P-channel open-drain output with pull-down resistor High-breakdownvoltage P-channel open-drain output with pull-down resistor TTL level input CMOS 3-state output High-breakdownvoltage P-channel open-drain output with pull-down resistor CMOS compatible input level
Non-Port Function
Related SFRS FLDC mode register 1 FLDC mode register 2 Port P0 segment/digit switch register FLDC mode register 1 FLDC mode register 2
Diagram No.
Port P0
Output
FLD automatic display function
(1)
P10/SEG40/ DIG8- P17/DIG15
Port P1
Output
FLD automatic display function
(1) (2)
P20/DIG16- P23/DIG19
Output Port P2 Input/output, individual bits
FLD automatic display function
FLDC mode register 1 FLDC mode register 2 Port P2 digit/port switch register
(3)
P24-P27
(4)
P30/SEG24- P37/SEG31
Port P3
Output
FLD automatic display function
FLDC mode register 1 FLDC mode register 2
(5)
P40/INT0 P45/INT1/ ZCR P42/INT2- P44/INT4 P41 P46/T1OUT, P47/T3OUT Port P4
Input
External interrupt input Zero cross detection circuit input (P45)
Interrupt edge selection register Zero cross detection control register
(6)
Input/output, individual bits
CMOS compatible input level CMOS 3-state output
(7) (4)
Timer output
Timer 12 mode register Timer 34 mode register
(8)
11
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pin P50/SIN2/ AN8 P51/SOUT2/ AN9, P52/SCLK2/ AN10 P53/SRDY2/ AN11 P54/SIN3/ AN12 P55/SOUT3/ AN13, P56/SCLK3/ AN14 P57/SRDY3/ AN15 P60 P61/PWM P62/CNTR0, P63/CNTR1 P64/SIN1 P65/SOUT1, P66/SCLK11 P67/SRDY1/ CS/SCLK12 P70/AN0- P77/AN7
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
Diagram No. (9)
Serial I/O2 function I/O A-D conversion input CMOS compatible input level CMOS 3-state output
Serial I/O2 control register AD/DA control register
(10)
(11) (9) Serial I/O3 function I/O A-D conversion input Serial I/O3 control register AD/DA control register (10)
Port P5
(11) Input/output, individual bits PWM (timer) output CMOS compatible input level CMOS 3-state output Timer input Timer 56 mode register Interrupt edge selection register Serial I/O1 control register Serial I/O automatic transfer control register AD/DA control register (4) (8) (7) (9) (10) (11)
Port P6
Serial I/O1 function I/O
Port P7
P80/SEG8- P87/SEG15
Port P8
P90/SEG16- P97/SEG23
Port P9
Output
PA0/SEG0- PA7/SEG7 PB0/XCOUT, PB1/XCIN PB2/DA PB3
Port PA
Input/output, individual bits
CMOS compatible input level CMOS 3-state output CMOS compatible input level High-breakdownvoltage P-channel open-drain output with pull-down resistor High-breakdownvoltage P-channel open-drain output with pull-down resistor CMOS compatible input level High-breakdownvoltage P-channel open-drain output CMOS compatible input level CMOS 3-state output
A-D conversion input
(12)
FLDC mode register Segment/port switch register FLD automatic display function FLDC mode register
(13)
(5)
FLDC mode register Segment/port switch register I/O for sub-clock generating circuit D-A conversion output
(13)
CPU mode register AD/DA control register
Port PB
Input/output, individual bits
(14) (15) (16) (4)
Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
12
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P10, P11 Shift signal from previous stage S/D switch register Blanking signal for key-scan Data bus Local data bus Dimmer signal (Note) Port latch
V
Shift signal to next stage
VEE
(2) Ports P12-P17 Shift signal from previous stage Dimmer signal (Note) Data bus Port latch
V
Shift signal to next stage
VEE
(3) Ports P20-P23 Shift signal from previous stage D/P switch register Dimmer signal (Note) Data bus Port latch
V
Blanking signal for key-scan Shift signal to next stage VEE
(4) Ports P24-P27, P41, P60, PB3 Direction register Data bus Port latch
V : High-breakdown-voltage P-channel transistor Note: The dimmer signal sets the Toff timing.
Fig. 4 Port block diagram (1)
13
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(5) Ports P3, P9 Dimmer signal (Note) Port latch
V
Local data bus Data bus
VEE (6) Ports P40, P45 Data bus
INT0, INT1 interrupt input Zero cross detection circuit input (only P45) (7) Ports P42-P44, P62, P63 Direction register Data bus Port latch
INT2-INT4 interrupt input CNTR0,CNTR1 input (8) Ports P46, P47, P61 Timer 1 output selection bit Timer 3 output selection bit Timer 6 output selection bit Direction register Data bus Port latch
Timer 1 output Timer 3 output Timer 6 output
V : High-breakdown-voltage P-channel transistor Note: The dimmer signal sets the Toff timing.
Fig. 5 Port block diagram (2)
14
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Ports P50, P54, P64 Direction register
Data bus
Port latch
Serial I/O input A-D conversion input Analog input pin selection bit (10) Ports P51, P52, P55, P56, P65, P66 P-channel output disable signal Output OFF control signal Serial I/O port selection bit Direction register Data bus Port latch
SOUT or SCLK Serial clock input (only P52, P56, P66) A-D conversion input Analog input pin selection bit (11) Ports P53, P57, P67 SRDY output enable bit Direction register
Data bus
Port latch
Serial ready output or SCLK
CS input (only P67)
A-D conversion input Analog input pin selection bit (12) Port P7 Direction register
Data bus
Port latch
A-D conversion input Analog input pin selection bit
Fig. 6 Port block diagram (3)
15
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(13) Ports P8, PA S/P switch register Dimmer signal (Note) Directionregister Port latch read
V
Local data bus Data bus
(14) Port PB0 Port XC switch bit Direction register Data bus Port latch
Oscillation circuit Port PB1 Port XC switch bit
(15) Port PB1
Port XC switch bit Direction register Data bus Port latch
Sub-clock generating circuit input (16) Port PB2 Direction register Data bus Port latch
D-A conversion output D-A output enable bit
V : High-breakdown-voltage P-channel transistor Note: The dimmer signal sets the Toff timing.
Fig. 7 Port block diagram (4)
16
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by 20 sources: 5 external, 14 internal, and 1 software.
Interrupt Operation
When an interrupt is received, the contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag is set to inhibit other interrupts from interfering. The corresponding interrupt request bit is cleared and the interrupt jump destination address is read from the vector table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I (interrupt disable) flag disables all interrupts except the BRK instruction interrupt. Table 1. Interrupt vector addresses and priority Interrupt Source Reset (Note 2) INT0 INT1/ZCR INT2 Remote control/ counter overflow Serial I/O1 Serial I/O automatic transfer Serial I/O2 Serial I/O3 Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 INT3 5 FFF516 FFF416 4 FFF716 FFF616 Priority 1 2 3 Vector Addresses (Note 1) High Low FFFD16 FFFC16 FFFB16 FFF916 FFFA16 FFF816
Notes on Use
When the active edge of an external interrupt (INT0 to INT4) is changed or when switching interrupt sources in the same vector address, the corresponding interrupt request bit may also be set. Therefore, please take following sequence; (1) Disable the external interrupt which is selected. (2) Change the active edge. (3) Clear the interrupt request bit which is selected to "0". (4) Enable the external interrupt which is selected.
Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1/ZCR input At detection of either rising or falling edge of INT2 input At 8-bit counter overflow At completion of data transfer At completion of the last data transfer At completion of data transfer At completion of data transfer At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At timer 5 underflow At timer 6 underflow At detection of either rising or falling edge of INT3 input At detection of either rising or falling edge of INT4 input At completion of A-D conversion At falling edge of the last digit immediately before blanking period starts At rising edge of each digit
Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when interrupt interval determination is operating Valid when serial I/O ordinary mode is selected Valid when serial I/O automatic transfer mode is selected Valid when serial I/O2 is selected Valid when serial I/O3 is selected STP release timer underflow
6 7 8 9 10 11 12 13 14
FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316
FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216
INT4
15
FFE116
FFE016
External interrupt (active edge selectable) Valid when INT4 interrupt is selected External interrupt (active edge selectable) Valid when A-D conversion interrupt is selected Valid when FLD blanking interrupt is selected Valid when FLD digit interrupt is selected Non-maskable software interrupt
A-D conversion FLD blanking 16 FLD digit BRK instruction 17 FFDD16 FFDC16 FFDF16 FFDE16
At BRK instruction execution
Notes 1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority.
17
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit Interrupt enable bit
Interrupt disable flag (I)
BRK instruction Reset
Interrupt request
Fig. 8 Interrupt control
b7
b0
Interrupt edge selection register (INTEDGE : address 003A 16) INT0 interrupt edge selection bit INT1/ZCR interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit INT4/AD conversion interrupt switch bit CNTR0 pin active edge switch bit CNTR1 pin active edge switch bit
0 : Falling edge active 1 : Rising edge active
0 : INT4 interrupt 1 : A-D conversion interrupt 0 : Rising edge count 1 : Falling edge count
b7
b0
Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1/ZCR interrupt request bit INT2 interrupt request bit Remote control/counter overflow interrupt request bit Serial I/O1 interrupt request bit Serial I/O automatic transfer interrupt request bit Serial I/O2 interrupt request bit Serial I/O3 interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit
b7
b0
Interrupt request register 2 (IREQ2 : address 003D16) Timer 3 interrupt request bit Timer 4 interrupt request bit Timer 5 interrupt request bit Timer 6 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit AD conversion interrupt request bit FLD blanking interrupt request bit FLD digit interrupt request bit Not used (returns "0" when read)
0 : No interrupt request issued 1 : Interrupt request issued
b7
b0
Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1/ZCR interrupt enable bit INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit Serial I/O1 interrupt enable bit Serial I/O automatic transfer interrupt enable bit Serial I/O2 interrupt enable bit Serial I/O3 interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit
b7
b0
Interrupt control register 2 (ICON2 : address 003F16) Timer 3 interrupt enable bit Timer 4 interrupt enable bit Timer 5 interrupt enable bit Timer 6 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit AD conversion interrupt enable bit FLD blanking interrupt enable bit FLD digit interrupt enable bit Not used (returns "0" when read) (do not write "1" to this bit)
0 : Interrupts disabled 1 : Interrupts enabled
Fig. 9 Structure of interrupt-related registers
18
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMERS
The 3819 group has 6 built-in timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. Each timer has the 8-bit timer latch. The timers count down. Once a timer reaches 0016, at the next count pulse the contents of each timer latch is loaded into the corresponding timer, and sets the corresponding interrupt request bit to "1". The count can be stopped by setting the stop bit of each timer to "1". The internal clock can be set to either the high-speed mode or low-speed mode with the CPU mode register. At the same time, timer internal count source is switched to either f(XIN) or f(XCIN).
Timer 1 and Timer 2
The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. A rectangular waveform of timer 1 underflow signal divided by 2 is output from the P46/T1OUT pin. The waveform polarity changes each time timer 1 overflows. The active edge of the external clock CNTR0 can be switched with the bit 6 of the interrupt edge selection register. At reset or when executing the STP instruction, all bits of the timer 12 mode register are cleared to "0", timer 1 is set to "FF16", and timer 2 is set to "0116".
Timer 3 and Timer 4
The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. A rectangular waveform of timer 3 underflow signal divided by 2 is output from the P47/T3OUT pin. The waveform polarity changes each time timer 3 overflows. The active edge of the external clock CNTR1 can be switched with the bit 7 of the interrupt edge selection register.
Timer 5 and Timer 6
The count sources of timer 5 and timer 6 can be selected by setting the timer 56 mode register. A rectangular waveform of timer 6 underflow signal divided by 2 is output from the P61/PWM pin. The waveform polarity changes each time timer 6 overflows.
Timer 6 PWM Mode
Timer 6 can output a rectangular waveform with duty cycle n/(n + m) from the P61/PWM pin by setting the timer 56 mode register (refer to fig. 12). The n is the value set in timer 6 latch (address 002516) and m is the value in the timer 6 PWM register (address 002716). If n is "0", the PWM output is "L", if m is "0", the PWM output is "H"(n=0 is prior than m=0). In the PWM mode, interrupts occur at the rising edge of the PWM output.
19
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus Timer 1 count Timer 1 latch (8) source "1" selection bit FF16 Timer 1 (8) "0" Timer 1 count stop bit
XCIN "1" XIN P46/T1OUT "0"
Internal system clock selection bit 1/16 P46 latch 1/2
RESET STP instruction Timer 1 interrupt request
Timer 1 output selection bit Timer 2 count Timer 2 latch (8) source "00" selection bit 0116 Timer 2 (8) "01" "10" Timer 2 count stop bit
P46 direction register
Timer 2 interrupt request
P62/CNTR0
Rising/falling edge switch
Timer 3 count Timer 3 latch (8) source "1" selection bit Timer 3 (8) P47/T3OUT P47 latch 1/2 Timer 3 output selection bit "0" Timer 3 count stop bit
Timer 3 interrupt request
P47 direction register
P63/CNTR1
Rising/falling edge switch
Timer 4 count Timer 4 latch (8) source "01" selection bit Timer 4 (8) "00" "10" Timer 4 count stop bit
Timer 4 interrupt request
Timer 5 count Timer 5 latch (8) source "1" selection bit Timer 5 (8) "0" Timer 5 count stop bit Timer 6 count Timer 6 latch (8) source "01" selection bit Timer 6 (8) "00" "10" Timer 6 count stop bit Timer 6 PWM register (8) P61/PWM P61 latch "1" Timer 6 output selection bit "0" PWM 1/2
Timer 5 interrupt request
Timer 6 interrupt request
Timer 6 operating mode selection bit
P61 direction register
Fig. 10 Timer block diagram
20
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Timer 12 mode register (T12M : address 002816) Timer 1 count stop bit 0 : Operating 1 : Stopped Timer 2 count stop bit 0 : Operating 1 : Stopped Timer 1 count source selection bit 0 : f(XIN)/16 or f(XCIN)/16 1 : f(XCIN) Not used (returns "0" when read) Timer 2 count source selection bits b5 b4 0 0 : Timer 1 underflow 0 1 : f(XCIN) 1 0 : External count input CNTR0 1 1 : Not available Timer 1 output selection bit (P46) 0 : I/O port 1 : Timer 1 output Not used (returns "0" when read)
b7
b0
Timer 34 mode register (T34M : address 002916) Timer 3 count stop bit 0 : Operating 1 : Stopped Timer 4 count stop bit 0 : Operating 1 : Stopped Timer 3 count source selection bit 0 : f(XIN)/16 or f(XCIN)/16 1 : Timer 2 underflow Not used (returns "0" when read) Timer 4 count source selection bits b5 b4 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : Timer 3 underflow 1 0 : External count input CNTR1 1 1 : Not available Timer 3 output selection bit (P47) 0 : I/O port 1 : Timer 3 output Not used (returns "0" when read)
b7
b0
Timer 56 mode register (T56M : address 002A16) Timer 5 count stop bit 0 : Operating 1 : Stopped Timer 6 count stop bit 0 : Operating 1 : Stopped Timer 5 count source selection bit 0 : f(XIN)/16 or f(XCIN)/16 1 : Timer 4 underflow Timer 6 operation mode selection bit 0 : Timer mode 1 : PWM mode Timer 6 count source selection bits b5 b4 0 0 : f(XIN)/16 or f(XCIN)/16 0 1 : Timer 5 underflow 1 0 : Timer 4 underflow 1 1 : Not available Timer 6 (PWM) output selection bit (P61) 0 : I/O port 1 : Timer 6 output Not used (returns "0" when read) (do not write "1")
Fig. 11 Structure of timer-related registers
21
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ts Timer 6 count source
Timer 6 PWM output n ! ts (n + m) ! ts m ! ts
Timer 6 interrupt request
Timer 6 interrupt request
Note: If the value set in timer 6 is n and the value set in the timer 6 PWM register is m, a PWM waveform with duty cycle n/(n + m) and period (n + m) 5 ts (ts : the frequency of the timer 6 count source) is output.
Fig. 12 Timing in timer 6 PWM mode
22
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SERIAL I/O
The 3819 group has built-in 8-bit clock synchronized serial I/O ! 3 channels (serial I/O1, serial I/O2, and serial I/O3). Serial I/O1 builds in the automatic transfer function. The function can be switched to the serial I/O ordinary mode with the serial I/O automatic transfer control register (address 001A16). Serial I/O2 and Serial I/O3 can be used only in the serial I/O ordinary mode. The I/O pins of the serial I/O function are also used as I/O ports P5 and P64-P67, and their operation is selected with the serial I/O control registers (addresses 001916, 001D16, and 001E16).
Serial I/O Control Registers (SIO1CON, SIO2CON, SIO3CON) 001916, 001D16, 001E16
Each of the serial I/O control registers (addresses 001916, 001D16, and 001E16) consists of 8 selection bits which control the serial I/O function.
23
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Main address bus
Local address bus
SI/O automatic transfer RAM (0F0016 to 0F1F16)
Main data bus
Local data bus
Address decorder
SI/O automatic transfer data pointer SI/O automatic transfer controller Serial I/O automatic transfer interrupt request
Internal system clock "1" selection bit "0" P67 latch (Note) SRDY1
XIN P67/SRDY1/ CS/SCLK12
Synchronization circuit
CS P66 latch "0" P66/SCLK11 "1" Serial I/O1 port selection bit "0" P65 latch P65/SOUT1 "1" Serial I/O1 port selection bit P64/SIN1
SCLK1
Internal synchronous "0" clock selection bit
External clock
Frequency divider
XCIN
SI/O automatic transfer interval register 1/8 1/16 1/32 1/64 Synchronous 1/128 clock selection 1/256 bit "1"
Serial I/O counter 1(3)
Serial I/O1 interrupt request
Serial I/O shift register 1(8)
P53/SRDY2
SRDY2 output selection bit
P53 latch "0" SRDY2 "1"
Synchronous clock selection bit "1"
Synchronization circuit
"0" P52 latch P52/SCLK2 "1" Serial I/O2 port selection bit "0" P51 latch P51/SOUT2 "1" Serial I/O2 port selection bit P50/SIN2
SCLK2
External clock
"0"
Frequency divider
1/8 1/16 1/32 1/64 1/128 1/256
Internal synchronous clock selection bit Serial I/O2 interrupt request
Serial I/O counter 2(3)
Serial I/O shift register 2(8)
P57/SRDY3
P57 latch "0" SRDY3 "1"
SRDY2 output selection bit
"1"
Synchronization circuit
"0" P56 latch P56/SCLK3 "1" Serial I/O3 port selection bit "0" P55 latch P55/SOUT3 "1" Serial I/O3 port selection bit P54/SIN3
SCLK3
External clock
"0"
Frequency divider
1/8 1/16 1/32 1/64 1/128 1/256
Internal synchronous clock selection bit Serial I/O3 interrupt request
Serial I/O counter 3(3)
Serial I/O shift register 3(8)
Note: Selected with the synchronous clock selection bit, SRDY1 output selection bit, serial I/O1 port selection bit (these 3 bits are of the serial I/O1 control register), automatic transfer control bit, and synchronous clock output pin selection bit (these 2 bits are ofthe serial I/O automatic transfer register).
Fig. 13 Serial I/O block diagram
24
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Serial I/O1 control register (SIO1CON(SC1) : address 001916) Internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 : f(XIN)/32 or f(XCIN)/32 0 1 1 : f(XIN)/64 or f(XCIN)/64 1 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 1 : f(XIN)/256 or f(XCIN)/256 Serial I/O1 port selection bit (P65, P66, and P67 V) 0 : I/O port 1 : SOUT1,SCLK11,and SCLK12 V output pins SRDY1 output selection bit (P67) 0 : I/O port 1 : SRDY1/CS V output pin (Note) Transfer direction selection bit 0 : LSB first 1 : MSB first Synchronous clock selection bit 0 : External clock 1 : Internal clock P65/SOUT1 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
b7
b0
Serial I/O2 control register (SIO2CON(SC2) : address 001D16) Internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 : f(XIN)/32 or f(XCIN)/32 0 1 1 : f(XIN)/64 or f(XCIN)/64 1 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 1 : f(XIN)/256 or f(XCIN)/256 Serial I/O2 port selection bit (P51, and P52) 0 : I/O port 1 : SOUT2 and SCLK2 output pins SRDY2 output selection bit (P53) 0 : I/O port 1 : SRDY2 output pin Transfer direction selection bit 0 : LSB first 1 : MSB first Synchronous clock selection bit 0 : External clock 1 : Internal clock P51/SOUT2 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
b7
b0
Serial I/O3 control register (SIO3CON(SC3) : address 001E16) Internal synchronous clock selection bits b2 b1 b0 0 0 0 : f(XIN)/8 or f(XCIN)/8 0 0 1 : f(XIN)/16 or f(XCIN)/16 0 1 0 : f(XIN)/32 or f(XCIN)/32 0 1 1 : f(XIN)/64 or f(XCIN)/64 1 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 1 : f(XIN)/256 or f(XCIN)/256 Serial I/O3 port selection bit (P55 and P56) 0 : I/O port 1 : SOUT3 and SCLK3 output pins SRDY3 output selection bit (P57) 0 : I/O port 1 : SRDY3 and SCLK3 output pins Transfer direction selection bit 0 : LSB first 1 : MSB first Synchronous clock selection bit 0 : External clock 1 : Internal clock P55/SOUT3 P-channel output disable bit 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
V
: Valid only in serial I/O automatic transfer mode. Note: When the external clock is selected in the serial I/O1 automatic transfer mode, the SRDY1 signal pin becomes the CS signal input pin.
Fig. 14 Structure of serial I/O control registers
25
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Serial I/O Ordinary Mode
Either an internal clock or an external clock can be selected as the synchronous clock for serial I/O transfer. A dedicated divider is built in as the internal clock for selecting of 6 clocks. If internal clock is selected, transfer starts with a write signal to a serial I/O register (addresses 001B16, 001F16, or 002616). After 8 bits have been transferred, the SOUT pin goes to high impedance state.
If external clock is selected, control the clock externally because the contents of the serial I/O register continue to shift during inputting the transfer clock. In this case, note that the SOUT pin does not go to high impedance state at the completion of data transfer. The interrupt request bit is set at the completion of the transfer of 8 bits, regardless of whether the internal or external clock is selected.
Synchronous clock Transfer clock Serial I/O register write signal (Note) Serial I/O output SOUT Serial I/O input SIN Receive enable signal SRDY Interrupt request bit set Note : If internal clock is selected, the SOUT pin goes to high impedance state at the completion of data transfer. D0 D1 D2 D3 D4 D5 D6 D7
Fig. 15 Serial I/O timing in the serial I/O ordinary mode (for LSB first)
(2) Serial I/O Automatic Transfer Mode
The serial I/O1 has the automatic transfer function. For automatic transfer, switch to the automatic transfer mode by setting the serial I/O automatic transfer control register (address 001A16). The following memory spaces and registers used to enable automatic transfer mode: * 32-byte serial I/O automatic transfer RAM * A serial I/O automatic transfer control register * A serial I/O automatic transfer interval register * A serial I/O automatic transfer data pointer When using serial I/O automatic transfer, set the serial I/O1 control register (address 001916) in the same way as the serial I/O ordinary mode. However, note that when external clock is selected, port P67 becomes the CS input pin by setting the bit 4 (the SRDY1 output selection bit ) of the serial I/O1 control register to "1".
b7 b0 Serial I/O automatic transfer control register (SIOAC : address 001A16) Automatic transfer control bit 0 : Serial I/O ordinary mode (serial I/O1 interrupt) 1 : Automatic transfer mode (serial I/O1 automatic transfer interrupt) Automatic transfer start bit 0 : Transfer completion 1 : Transferring(starts by writing "1") Transfer mode switch bit 0 : Fullduplex(transmit and receive) mode 1 : Transmit-only mode Synchronous clock output pin selection bit 0 : SCLK11 1 : SCLK12 Not used (return "0" when read)
Serial I/O Automatic Transfer Control Register (SIOAC) 001A16
The serial I/O automatic transfer control register (address 001A16) consists of 4 bits which control automatic transfer.
Fig. 16 Structure of serial I/O automatic transfer control register
26
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O Automatic Transfer Data Pointer (SIODP) 001816
The serial I/O automatic transfer data pointer (address 001816) consists of 5 bits which indicate addresses in serial I/O automatic transfer RAM (the value which adds 0F0016 to the serial I/O automatic transfer data pointer is actual address in memory). Set the value (the number of transfer data-1) to the serial I/O automatic transfer data pointer for specifying the storage address of first data.
q Setting of Serial I/O Automatic Transfer Data
When data is stored in the serial I/O automatic transfer RAM, store the first data at the address set with the serial I/O automatic transfer data pointer so that the last data can be stored at address 0F0016.
Serial I/O Automatic Transfer Interval Register (SIOAI) 001C16
The serial I/O automatic transfer interval register (address 001C16) consists of a 5-bit counter that determines the transfer interval Ti during automatic transfer. When writing the value n to the serial I/O automatic transfer interval register, Ti=(n+2) ! Tc (Tc: the length of one bit of the transfer clock) occurs. However, note that this transfer interval setting is valid only when selecting the internal clock as the clock source.
q Serial I/O Automatic Transfer RAM
The serial I/O automatic transfer RAM is the 32 bytes from address 0F0016 to address 0F1F16.
Address
Bit
7
6
5
4
3
2
1
0
0F0016 0F0116 0F0216
0F1D16 0F1E16 0F1F16
Fig. 17 Bit allocation of serial I/O automatic transfer RAM
Transfer clock
Serial I/O output SOUT Serial I/O input SIN
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DI0 TC
DI1
DI2
DI3
DI4
DI5
DI6
DI7
1-byte data
Ti
Fig. 18 Serial I/O automatic transfer interval timing
27
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Setting of Serial I/O Automatic Transfer Timing
The timing of serial I/O automatic transfer is set with the serial I/O1 control register (address 001916) and the serial I/O automatic transfer interval register (address 001C16). The serial I/O1 control register sets the transfer clock speed, and the serial I/O automatic transfer interval register sets the serial I/O automatic transfer interval. This setting of transfer interval is valid only when selecting the internal clock as the clock source.
(2.1) Operation in Full Duplex Mode
In full duplex mode, data can be transmitted and received at the same time. Data in the automatic transfer RAM is transmitted in sequence in accordance with the serial I/O automatic transfer data pointer and simultaneously reception data is written to the automatic transfer RAM. The transfer timing of each bit is the same as that in ordinary operation mode, and the transfer clock stops at "H" after eight transfer clocks are counted. When selecting the internal clock, the transfer clock remains at "H" for the time set with the serial I/O automatic transfer interval register, then the data at the next address (the address is indicated with the serial I/O automatic transfer data pointer) are transferred. If when selecting the external clock, the setting of the automatic transfer interval register is invalid, so control the transfer clock externally. The last data transfer completes when the contents of the serial I/O automatic transfer pointer reach "0016". At that point, the serial I/O automatic transfer interrupt request bit is set to "1" and the bit 1 of the serial I/O automatic transfer control register is cleared to "0" to complete the serial I/O automatic transfer.
q Start of Serial I/O Automatic Transfer
Automatic transfer mode is set by writing "1" to the bit 0 of the serial I/O automatic transfer control register (address 001A16), then automatic transfer starts by writing "1" to the bit 1. The bit 1 of the serial I/O automatic transfer control register is always "1" during automatic transfer; writing "0" can complete the serial I/O automatic transfer.
q Operation in Serial I/O Automatic Transfer Modes
There are two modes for serial I/O automatic transfer: full duplex mode and transmit-only mode. Either internal or external clock can be selected for each of these modes.
(2.2) Operation in Transmit-Only Mode
The operation in transmit-only mode is the same as that in full duplex mode, except for that data is not transferred from the serial I/O1 register to the serial I/O automatic transfer RAM.
Transfer direction selection bit
LSB first (SC15 = "0" ) : MSB MSB first (SC15 = "1" ) : LSB DO7 DO6 SIN DI0 DO5 DO4
LSB MSB DO3 DO2 DO1 DO0 SOUT DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO7 DO6 DO5 DO4 DO3 DO2
DI1
DI0
DI2
DI1
DI0
DO7 DO6 DO5 DO4 DO3
* * *
DI7 Transfer clock
DI6
DI5
DI4
DI3
DI2
DI1
DI0
Serial I/O1 register
Fig. 19 Serial I/O1 register transfer operation in full duplex mode
28
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2.3) When Selecting the Internal Clock
When selecting the internal clock, the P67/SRDY1/CS/SCLK12 pin can be used as the SRDY1 pin by setting SC14 to "1". When selecting the internal clock, the P67 pin can be used as the synchronous clock output pin SCLK12 by setting SIOAC3 to "1". In this case, the SCLK11 pin goes to high impedance state. Select the function of the P67/SRDY1/CS/SCLK12 and P66/SCLK11 with the following registers (refer to Table 2): qthe bit 3 (SC13), the bit 4(SC14), and the bit 6(SC16) of the serial I/O1 control register qthe bit 3 (SIOAC3) of the serial I/O automatic transfer control register
When using both the SCLK11 and SCKL12 by switching, switch the P67/SRDY1/CS/SCLK12 to the P67 (SC14=0) and set the P67 direction register to input mode. Note that switch SIOAC3 during "H" of transfer clock at the completion of automatic transfer. Table 2. SCLK11 and SCLK12 selection SC16 1 SC14 0 SC33 1 SIOAC3 P66/SCLK11 P67/SCLK12 0 SCLK11 P67 High 1 impedance SCLK12
Note : SC13: Serial I/O1 port selection bit SC14: SRDY1 output selection bit SC16: Synchronous clock selection bit SIOAC3: Synchronous clock output pin selection bit
Bit 1 write signal of serial I/O automatic transfer control register Bit 1 of serial I/O automatic transfer control register Write signal from RAM to serial I/O1 register Write signal from serial I/O1 register to RAM Data pointer Transfer clock (internal or SCLK output) Receive enabled signal SRDY Serial I/O output Sout Serial I/O input SIN DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO0 DI0 DO6 DO7 DI6 DI7 n n-1 0
Transfer interval
Fig. 20 Timing diagram during serial I/O automatic transfer (internal clock selected, SRDY used)
Bit 1 write signal of serial I/O automatic transfer control register Bit 1 of serial I/O automatic transfer control register Write signal from RAM to serial I/O1 register Write signal from serial I/O1 register to RAM Data pointer Bit 3 of serial I/O automatic transfer control register Transfer clock (internal) SCLK11 output SCLK12 output Serial I/O output Sout Serial I/O input SIN
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO0 DO6 DO7 DO0 DO1 DO2 DO3
m
m-1
0
n
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI0
DI6
DI7
DI0
DI1
DI2
DI3
Transfer interval
Fig. 21 Timing during serial I/O automatic transfer (internal clock selected, SCLK11 and SCLK12 used)
29
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2.4) When Selecting the External Clock
When selecting the external clock, the internal clock and the setting of transfer interval with the serial I/O automatic transfer interval register are invalid, but the serial I/O output pin SOUT1 and the internal transfer clock can be controlled from the outside by setting the SRDY1 pin to the CS (input) pin. When the CS input is "L", the SOUT1 pin and the internal transfer clock are enabled. When the CS input is "H", the SOUT1 pin goes to high impedance state and the internal transfer clock goes to "H". Select the function of the P67/SRDY1/CS/SCLK12 with the following registers (refer to Table GA-2): qthe bit 4 (SC14) and the bit 6 (SC16) of the serial I/O1 control register qthe bit 0 (SIOAC0) of the serial I/O automatic transfer control register Switch the CS pin from "L" to "H" or from "H" to "L" during "H" of the transfer clock (SCLK11 input) after transferring 1-byte data. When selecting the external clock, set the external clock to "L" after 9 cycles or more of the internal clock after setting the start bit. After transferring 1-byte data, leave 11 cycles or more of the internal clock free for the transfer interval.
When not using the CS input, note that the SOUT pin will not go to high impedance state, even after transfer is completed. When not using the CS input, or when CS is "L", control the external clock because the data in the serial I/O register will continue to shift while the external clock is input, even after the completion of automatic transfer (Note that the automatic transfer interrupt request bit is set and the bit 1 of the serial I/O automatic transfer register is cleared at the point when the specified number of bytes of data have been transferred.) Table 3. P67/SRDY1/CS selection SC16 0 SC14 0 1 SIOAC0 ! 0 1 P67/SRDY1/CS P67 SRDY1 CS
Note : SC14: SRDY1 output selection bit SC16: Synchronous clock selection bit SIOAC0: Automatic transfer control bit
Bit 1 write signal of serial I/O automatic transfer control register Bit 1 of serial I/O automatic transfer control register Write signal from RAM to serial I/O1 register Write signal from serial I/O1 register to RAM Data pointer External input CS Transfer clock SCLK input Transfer clock (internal) Serial I/O output SOUT Serial I/O input SIN X DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 X X X X X n n-1
Note: Data marked with X is invalid.
Fig. 22 Timing during serial I/O automatic transfer (external clock selected)
30
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
The functional blocks of the A-D converter are described below.
b7 b0 AD/DA control register (ADCON : address 002C16) Analog input pin selection bits b3 b2 b1 b0 0 0 0 0 : P70/AN0 0 0 0 1 : P71/AN1 0 0 1 0 : P72/AN2 0 0 1 1 : P73/AN3 0 1 0 0 : P74/AN4 0 1 0 1 : P75/AN5 0 1 1 0 : P76/AN6 0 1 1 1 : P77/AN7 1 0 0 0 : P50/SIN2/AN8 1 0 0 1 : P51/SOUT2/AN9 1 0 1 0 : P52/SCLK2/AN10 1 0 1 1 : P53/SRDY2/AN11 1 1 0 0 : P54/SIN3/AN12 1 1 0 1 : P55/SOUT3/AN13 1 1 1 0 : P56/SCLK3/AN14 1 1 1 1 : P57/SRDY3/AN15 AD conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read) DA output enable bit 0 : Disable 1 : Enable Not used (returns "0" when read)
A-D Conversion Register (AD) 002D16
The A-D conversion register is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion.
AD/DA Control Register (ADCON) 002C16
The AD/DA control register controls the A-D and the D-A conversion process. Bits 0 to 3 of this register select analog input pins. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conversion is completed. The A-D conversion starts by writing "0" to this bit. Bit 6 controls the output of D-A converter.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between AVSS and VREF by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P77/AN7-P70/ AN0, P57/SRDY3/AN15-P50/SIN2/AN8, and inputs to the comparator.
Fig. 23 Structure of A-D control register
Comparator and Control Circuit
The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1". Note that the comparator is constructed linked to a capacitor, so set f(XIN) to 500 kHz or more during A-D conversion.
Note : When using the A-D conversion interrupt, set the INT4/AD conversion interrupt switch bit (the bit 5 of the interrupt selection register) to "1".
31
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
b7 AD-DA control register (address 002C16) 4 P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 P50/SIN2/AN8 P51/Sout2/AN9 P52/SCLK2 /AN10 P53/SRDY2/AN11 P54/SIN3/AN12 P55/SOUT3/AN13 P56/SCLK3 /AN14 P57/SRDY3/AN15 A-D control circuit
b0
A-D conversion interrupt request
Channel selector
Comparator
A-D conversion register (Address 002D16) 8 Resistor ladder
VREF
AVSS
Fig. 24 A-D converter block diagram
D-A CONVERTER
The 3819 group has internal D-A converter with 8-bit resolutions ! 1 channel. D-A conversion is performed by setting the value in the D-A conversion register. The result of D-A conversion is output from the DA pin by setting the DA output enable bit to "1" . At this time, the corresponding bit (PB2/DA) of the port PB direction register should be set to "0" (input status). The output analog voltage V is determined with the value n (n: decimal number) in the D-A conversion register as follows: V=VREF ! n/256 (n=0 to 255) VVREF: the reference voltage At reset, the D-A conversion register is cleared to "0016", the DA output enable bits are cleared to "0", and the PB2/DA pin goes to high impedance state. The D-A output does not build in a buffer, so connect an external buffer when driving a low-impedance load. Set VCC to 3.0 V or more when using the D-A converter.
Data bus
D-A conversion register (8) DA output enable bit R-2R resistor ladder PB2/DA
Fig. 25 D-A converter block diagram
"0" DA output enable bit PB2/DA "1" MSB D-A conversion register AVSS VREF "0" "1" 2R
R 2R
R 2R
R 2R
R 2R
R 2R
R 2R
R 2R LSB
2R
Fig. 26 Equivalent connection circuit of D-A converter
32
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLD CONTROLLER
The 3819 group has fluorescent display (FLD) drive and control circuits. The FLD controller consists of the following components: * 42 pins for segments * 20 pins for digits * FLDC mode register 1 * FLDC mode register 2 * FLD data pointer * FLD data pointer reload register
* Port P0 segment/digit switch register * Port P2 digit/port switch register * Port PA segment/port switch register * Port P8 segment/port switch register * 96-byte FLD automatic display RAM The segment pins can be used from 16 up to 42 pins (maximum) and the digit pins can be used from 6 up to 16 pins (maximum). The segment and the digit pins can be used up to 52 pins (maximum) in total. In the FLD automatic display mode ports P12 to P17 become digit pins DIG10 to DIG15 automatically.
Main address bus
FLD automatic display RAM 0F8016 G1 (SEG PA)
G2 (SEG PA)
Main data bus
Local data bus
S/P S/P S/P S/P S/P S/P S/P S/P PA0/SEG0 PA1/SEG1 PA2/SEG2 PA3/SEG3 PA4/SEG4 PA5/SEG5 PA6/SEG6 PA7/SEG7
8
G15 (SEG PA)
0F8F16 G16 (SEG PA) 0F9016 G1 (SEG P8) Local address bus
G2 (SEG P8)
003516
S/P S/P S/P S/P S/P S/P S/P S/P
001416
P80/SEG8 P81/SEG9 P82/SEG10 P83/SEG11 P84/SEG12 P85/SEG13 P86/SEG14 P87/SEG15
G15 (SEG P8)
0F9F16 G16 (SEG P8) 0FA016 G1 (SEG P9)
G2 (SEG P9)
8
003416
G15 (SEG P9) 0FAF16 G16 (SEG P9) 0FB016 G1 (SEG P3) G2 (SEG P3)
001016
P90/SEG16 P91/SEG17 P92/SEG18 P93/SEG19 P94/SEG20 P95/SEG21 P96/SEG22 P97/SEG23
8
G15 (SEG P3)
0FBF16 G16 (SEG P3) 0FC016 G1 (SEG P0)
G2 (SEG P0)
001216
P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31
8
G15 (SEG P0) 0FCF16 G16 (SEG P0) 0FD016 G1 (SEG P1) G2 (SEG P1) S/D S/D S/D S/D S/D S/D S/D S/D
000616
G15 (SEG P1) P00/SEG32/DIG0 P01/SEG33/DIG1 P02/SEG34/DIG2 P03/SEG35/DIG3 P04/SEG36/DIG4 P05/SEG37/DIG5 P06/SEG38/DIG6 P07/SEG39/DIG7
0FDF16 G16 (SEG P1)
8
003216 FLD data pointer reload register (address 003816)
000016
S/D P10/SEG40/DIG8 S/D P11/SEG41/DIG9 P12/DIG10 P13/DIG11 P14/DIG12 P15/DIG13 P16/DIG14 P17/DIG15
8
Address decoder
FLD data pointer (address 003816)
FLDC mode 003716 register 1 (address 003616)
D/P D/P D/P D/P P20/DIG16 P21/DIG17 P22/DIG18 P23/DIG19
000216
4
Timing generator
003316 000416 FLD blanking interrupt FLD digit interrupt
Fig. 27 FLD control circuit block diagram
33
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FLDC Mode Registers (FLDM 1, FLDM 2) 003616, 003716
The FLDC mode register 1 (address 003616) and FLDC mode register 2 (address 003716) are a seven bit register and an eight bit
b7 b0
register respectively which are used to control the FLD automatic display and set the blanking time Tscan for key-scan.
FLDC mode register 1 (FLDM 1 : address 003616) Tscan control bits
b1 b0
0 0 : 0 FLD digit interrupt (at rising edge of each digit) 0 1 : 1 ! Tdisp 1 0 : 2 ! Tdisp FLD blanking interrupt (at falling edge of the last digit) 1 1 : 3 ! Tdisp Toff control bits (Setting of digit/segment OFF time)
b5 b4 b3 b2
0 0 0 0 : 1/16 ! Tdisp 0 0 0 1 : 2/16 ! Tdisp 0 0 1 0 : 3/16 ! Tdisp 0 0 1 1 : 4/16 ! Tdisp 0 1 0 0 : 5/16 ! Tdisp 0 1 0 1 : 6/16 ! Tdisp 0 1 1 0 : 7/16 ! Tdisp 0 1 1 1 : 8/16 ! Tdisp 1 0 0 0 : 9/16 ! Tdisp 1 0 0 1 : 10/16 ! Tdisp 1 0 1 0 : 11/16 ! Tdisp 1 0 1 1 : 12/16 ! Tdisp 1 1 0 0 : 13/16 ! Tdisp 1 1 0 1 : 14/16 ! Tdisp 1 1 1 0 : 15/16 ! Tdisp 1 1 1 1 : 16/16 ! Tdisp Not used (returns "0" when read) High-breakdown-voltage drivability selection bit 0 : Strong drivability 1 : Weak drivability
Fig. 28 Structure of FLDC mode register 1
b7
b0 FLDC mode register 2 (FLDM 2 : address 003716) Automatic display control bit(P0, P1, P20-P23, P3, P8, P9, PA) 0 : Ordinary mode 1 : Automatic display mode Display start bit 0 : Display stopped 1 : Display in progress (display starts by writing "1" to this bit which is set to "0") Tdisp control bits (digit time setting, at 8 MHz oscillation frequency) 0 : 128 s 1 : 256 s 0 : 384 s 1 : 512 s 0 : 640 s 1 : 768 s 0 : 896 s 1 : 1024 s 0 : 1152 s 1 : 1280 s 0 Not available 1111 Pl0 segment/digit switch bit 0 : Digit 1 : Segment Pl1 segment/digit switch bit 0 : Digit 1 : Segment 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1
b5 b4 b3 b2
Fig. 29 Structure of FLDC mode register 2
34
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Pins for FLD Automatic Display
Ports P0, P1, P20-P23, P3, P8, P9, and PA is selected for the FLD automatic display function by setting the automatic display control bit of the FLDC mode register 2 (address 003716) to "1". Table 4. Pins in FLD automatic display mode Port Name PA0-PA7 Automatic Display Pins SEG0-SEG7 or PA0-PA7 SEG8-SEG15 or P80-P87 SEG16-SEG23 SEG24-SEG31 SEG32-SEG41 or DIG0-DIG9 DIG10-DIG15 DIG16-DIG19 or P20-P23
When using the FLD automatic display mode, set the number of segments and digits for each port.
Setting Method The individual bits of the segment/port switch register (address 003516) can be set each pin to either segment ("1") or general-purpose I/O port ("0").
P80-P87 P90-P97 P30-P37 P00-P07 P10, P11 P12-P17 P20-P23
The individual bits of the segment/port switch register (address 003416) can be used to set each pin to either segment ("1") or general-purpose I/O port ("0"). None (segment only) None (segment only) The individual bits of the segment/digit switch register (address 003216) and the bit 6, 7 of the FLDC mode register 2 can be used to set each pin to segment ("1") or digit ("0"). (Note) None (digit only) The individual bits of the digit/port switch register (address 003316) can be used to set each pin to digit ("1") or general-purpose output port ("0"). (Note)
Note : Be sure to set digits in sequence.
Number of segments Number of digits Port PA 0 (has the segment/port 0 switch register) 0 0 0 0 0 0
24 8 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
0 0 0 0 0 0 0 0
30 10 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
1 1 1 1 1 1 1 1
36 16 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
Number of segments Number of digits Port P3 (segment only)
24 8 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
30 10 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
36 16 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31
Port P8 0 P80 (has the segment/port 0 P81 switch register) 0 P82 0 P83 0 P84 0 P85 0 P86 0 P87 Port P9 (segment only)
0 0 0 0 1 1 1 1
P80 P81 P82 P83 SEG12 SEG13 SEG14 SEG15
1 1 1 1 1 1 1 1
SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
Port P0 1 SEG32 (has the segment/digit 1 SEG33 switch register) 1 SEG34 1 SEG35 1 SEG36 1 SEG37 1 SEG38 1 SEG39 Port P1 0 DIG8 (has the segment/digit 0 DIG9 switch register) DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 Port P2 (has the digit/port switch register) 0 0 0 0 P20 P21 P22 P23
1 1 1 1 1 1 1 1
SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39
1 1 1 1 0 0 0 0
SEG32 SEG33 SEG34 SEG35 DIG4 DIG5 DIG6 DIG7
G16 G15 G14 G13
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
G8 G7 G6 G5 G4 G3 G2 G1
1 SEG40 1 SEG41 DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 1 1 1 1 DIG16 DIG17 DIG18 DIG19
G10 G9 G8 G7 G6 G5 G4 G3 G2 G1
0 DIG8 0 DIG9 DIG10 DIG11 DIG12 DIG13 DIG14 DIG15 1 1 1 1 DIG16 DIG17 DIG18 DIG19
G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1
Fig. 30 Segment/digit setting example
35
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q FLD Automatic Display RAM
The FLD automatic display RAM area is the 96 bytes from addresses 0F8016 to 0FDF16. The FLD automatic display RAM area can store 6-byte segment data up to 16 digits (maximum). Addresses 0F8016 to 0F8F16 are used for PA segment data, addresses 0F9016 to 0F9F16 are used for P8 segment data, addresses 0FA016 to 0FAF16 are used for P9 segment data, addresses 0FB016 to 0FBF16 are used for P3 segment data, addresses 0FC016 to 0FCF16 are used for P0 segment data, and addresses 0FD0 to 0FDF16 are used for P1 segment data.
FLD Data Pointer and FLD Data Pointer Reload Register (FLDDP) 003816
Both the FLD data pointer and FLD data pointer reload register are 7-bit registers allocated at address 003816. When writing data to this address, the data is written to the FLD data pointer reload register, when reading data from this address, the value in the FLD data pointer is read.
The FLD data pointer indicates the data address in the FLD automatic display RAM to be transferred to a segment. The FLD data pointer reload register indicates the first digit address of the most significant segment. The value which adds 0F8016 to these data is actual address in memory. The contents of the FLD data pointer indicate the first address of segment P1(the contents of the FLD data pointer reload register) at the start of automatic display. The FLDC data pointer content changes repeatedly as follows: when transferring the segment P1 data to the segment, the content decreases by -16; when transferring the segment P0 data, it decreases by -16; when transferring the segment P3 data, it decreases by -16; when transferring the segment P9 data, it decreases by -16; when transferring the segment P8 data, it decreases by -16; when transferring the segment PA data, it increases by +79. Once it reaches "00", at the next timing the value in the FLD data pointer reload register is transferred to the FLD data pointer. In this way, the 6-byte data of P1, P0, P3, P9, P8 and PA segments for 1 digit are transferred.
36
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bit Address 0F8016 0F8116
* * * * * * * * * * * * * * * * * *
7 SEG7 SEG7
6 SEG6 SEG6
5 SEG5 SEG5
4 SEG4 SEG4
* * * * * * * * *
3 SEG3 SEG3
2 SEG2 SEG2
1 SEG1 SEG1
0 SEG0 SEG0 The last digit (The last data of segment PA) Segment PA data area
0F8E16 0F8F16 0F9016 0F9116
* * * * * * * * * * * * * *
SEG7 SEG7 SEG15 SEG15
SEG6 SEG6 SEG14 SEG14
SEG5 SEG5 SEG13 SEG13
SEG4 SEG4 SEG12 SEG12
* * * * * * *
SEG3 SEG3 SEG11 SEG11
SEG2 SEG2 SEG10 SEG10
SEG1 SEG1 SEG9 SEG9
SEG0 SEG0 SEG8 SEG8
The last digit (The last data of segment P8) Segment P8 data area
0F9E16 0F9F16 0FA016 0FA116
* * * * * * * * * * * * * *
SEG15 SEG15 SEG23 SEG23
SEG14 SEG14 SEG22 SEG22
SEG13 SEG13 SEG21 SEG21
SEG12 SEG12 SEG20 SEG20
* * * * * * *
SEG11 SEG11 SEG19 SEG19
SEG10 SEG10 SEG18 SEG18
SEG9 SEG9 SEG17 SEG17
SEG8 SEG8 SEG16 SEG16 The last digit (The last data of segment P9) Segment P9 data area
0FAE16 0FAF16 0FB016 0FB116
* * * * * * * * * * * * * *
SEG23 SEG23 SEG31 SEG31
SEG22 SEG22 SEG30 SEG30
SEG21 SEG21 SEG29 SEG29
SEG20 SEG20 SEG28 SEG28
* * * * * * *
SEG19 SEG19 SEG27 SEG27
SEG18 SEG18 SEG26 SEG26
SEG17 SEG17 SEG25 SEG25
SEG16 SEG16 SEG24 SEG24
The last digit (The last data of segment P3) Segment P3 data area
0FBE16 0FBF16 0FC016 0FC116
* * * * * * * * * * * * * *
SEG31 SEG31 SEG39 SEG39
SEG30 SEG30 SEG38 SEG38
SEG29 SEG29 SEG37 SEG37
SEG28 SEG28 SEG36 SEG36
* * * * * * *
SEG27 SEG27 SEG35 SEG35
SEG26 SEG26 SEG34 SEG34
SEG25 SEG25 SEG33 SEG33
SEG24 SEG24 SEG32 SEG32
The last digit (The last data of segment P0) Segment P0 data area
0FCE16 0FCF16 0FD016 0FD116
* * * * * * * * * * * * * *
SEG39 SEG39
SEG38 SEG38
SEG37 SEG37
SEG36 SEG36
SEG35 SEG35
SEG34 SEG34
SEG33 SEG33 SEG41 SEG41
SEG32 SEG32 SEG40 SEG40 The last digit (The last data of segment P1) Segment P1 data area
* * * * * * *
0FDE16 0FDF16
SEG41 SEG41
SEG40 SEG40
Fig. 31 FLD automatic display RAM and bit allocation
37
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Data Setup
When data is stored in the FLD automatic display RAM, the last data of segment PA is stored at address 0F8016, the last data of segment P8 is stored at address 0F9016, the last data of segment P9 is stored at address 0FA016, the last data of segment P3 is stored at address 0FB016, the last data of segment P0 is stored at address 0FC016, and the last data of segment P1 is stored at address 0FD016 to allocate in se-
quence from the last data respectively. The first data of the segment PA, P8, P9, P3, P0, and P1 is stored at an address which adds the value of (the digit number-1) to the corresponding address 0F8016, 0F9016, 0FA016, 0FB016, 0FC016, and 0FD016. Set the low-order 4 bits of the FLD data pointer reload register to the value given by the number of digits-1. "1" is always written to bit 6 and bit 4, and "0" is always written to bit 5. Note that "0" is always read from bits 6, 5 and 4 when reading.
For 30 segments and 15 digits (FLD data pointer reload register = 14)
For 30 segments and 15 digits (FLD data pointer reload register = 14) Bit Address 0F8016 0F8116 0F8216 0F8316 0F8416 0F8516 0F8616 0F8716 0F8816 0F8916 0F8A16 0F8B16 0F8C16 0F8D16 0F8E16 0F8F16 0F9016 0F9116 0F9216 0F9316 0F9416 0F9516 0F9616 0F9716 0F9816 0F9916 0F9A16 0F9B16 0F9C16 0F9D16 0F9E16 0F9F16 0FA016 0FA116 0FA216 0FA316 0FA416 0FA516 0FA616 0FA716 0FA816 0FA916 0FAA16 0FAB16 0FAC16 0FAD16 0FAE16 0FAF16 Note : 7 6 5 4 3 2 1 0
Bit Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16
7
6
5
4
3
2
1
0
Shaded areas are used.
Fig. 32 Example of using the FLD automatic display RAM (1)
38
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
For 42 segments and 8 digits (FLD data pointer reload register = 7) Bit Address 0F8016 0F8116 0F8216 0F8316 0F8416 0F8516 0F8616 0F8716 0F8816 0F8916 0F8A16 0F8B16 0F8C16 0F8D16 0F8E16 0F8F16 0F9016 0F9116 0F9216 0F9316 0F9416 0F9516 0F9616 0F9716 0F9816 0F9916 0F9A16 0F9B16 0F9C16 0F9D16 0F9E16 0F9F16 0FA016 0FA116 0FA216 0FA316 0FA416 0FA516 0FA616 0FA716 0FA816 0FA916 0FAA16 0FAB16 0FAC16 0FAD16 0FAE16 0FAF16 Note : 7 6 5 4 3 2 1 0
For 42 segments and 8 digits (FLD data pointer reload register = 7) Bit Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16 0FD016 0FD116 0FD216 0FD316 0FD416 0FD516 0FD616 0FD716 0FD816 0FD916 0FDA16 0FDB16 0FDC16 0FDD16 0FDE16 0FDF16 7 6 5 4 3 2 1 0
Shaded areas are used.
Fig. 33 Example of using the FLD automatic display RAM (2) (continued)
39
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
q Timing Setting
The digit time (Tdisp) can be set with the FLDC mode register 2 (address 003716). The Tscan and digit/segment OFF time (Toff) can be set with the FLDC mode register 1 (address 003616). Note that flickering will occur if the repetition frequency (1/ (Tdisp ! number of digits + Tscan)) is an integral multiple of the digit timing Tdisp.
During automatic display bit 1 of the FLDC mode register 2 always keeps "1", automatic display can be interrupted by writing "0" to the bit 1.
q Key-scan
If key-scan is performed with the segment during the key-scan blanking period Tscan, take the following sequence: 1. Write "0" to the bit 0 (automatic display control bit) of the FLDC mode register 2 (address 003716). 2. Set the port corresponding to the segment for key-scan to the output port. 3. Perform the key-scan. 4. After the key-scan is performed, write "1" (automatic display mode) to the bit 0 of FLDC mode register 2 (address 003716). Note on performance of key-scan in the above 1 to 4 sequence. 1. Do not write "0" to the bit 1 of FLDC mode register 2 (address 003716). 2. Do not write "1" to the port corresponding to the digit.
q FLD Automatic Display Start
To perform FLD automatic display, set the following registers. * Port P0 segment/digit switch register * Port P2 digit/port switch register * Port P8 segment/port switch register * Port PA segment/port switch register * FLDC mode register 1 * FLDC mode register 2 * FLD data pointer Automatic display mode is selected by writing "1" to the bit 0 of the FLDC mode register 2 (address 003716), and the automatic display is started by writing "1" to the bit 1.
Tdisp
Tscan
Gn G n-1 G n-2
G1
Segment output Segment setting by software FLD digit interrupt occurs at the rising edge of each digit FLD blanking interrupt occurs at the falling edge of the last digit
Digit
Segment
Toff Tdisp
Fig. 34 FLDC timing
40
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPT INTERVAL DETERMINATION FUNCTION
The 3819 group builds in an interrupt interval determination circuit. This interrupt interval determination circuit has an 8-bit binary up counter. Using this counter, it determines a duration of time from the rising transition (falling transition) of an input signal pulse on the P42/INT2 pin to the rising transition (falling transition) of the signal pulse that is input next. How to determine the interrupt interval is described below. Enable the INT2 interrupt by setting the bit 2 of the interrupt control register 1 (address 003E16). Select the rising interval or falling interval by setting the bit 2 of the interrupt edge selection register (address 003A16). Set the bit 0 of the interrupt interval determination control register (address 003116) to "1" (interrupt interval determination operating). Select the sampling clock of 8-bit binary up counter by setting the bit 1 of the interrupt interval determination control register. When writing "0", f(XIN)/256 is selected (the sampling interval: 32 s at f(XIN) = 8.38 MHz) ; when "1", f(XIN)/512 is selected (the sampling interval: 64 s at f(XIN) = 8.38 MHz). When the signal of polarity which is set on the INT2 pin (rising or falling transition) is input, the 8-bit binary up counter starts counting up of the selected counter sampling clock. When the signal of polarity above is input again, the value of the 8-bit binary up counter is transferred to the interrupt interval
determination register (address 003016), and the remote control interrupt request occurs. Immediately after that, the 8-bit binary up counter is cleared to "0016". The 8-bit binary up counter continues to count up again from "0016". When count value reaches "FF16", the 8-bit binary up counter stops counting up. Then, simultaneously when the next counter sampling clock is input, the counter sets value "FF16" to the interrupt interval determination register to generate the counter overflow interrupt request.
Noise filter
The P42/INT2 pin builds in the noise filter. The noise filter operation is described below. Select the sampling clock of the input signal with the bits 2 and 3 of the interrupt interval determination control register. When not using the noise filter, set "002". The P42/INT2 input signal is sampled in synchronization with the selected clock. When sampling the same level signal in series, the signal is recognized as the interrupt signal, and the interrupt request occurs. When setting the bit 4 of interrupt interval determination control register to "1", the interrupt request can occur at both rising and falling edges. When using the noise filter, set the minimum pulse width of the INT2 input signal to 2 cycles or more.
Note : In the low-speed mode (CM7=1), the interrupt interval determination function can not operate.
The counter sampling clock selection bit
f(XIN)/256 f(XIN)/512
8-bit binary up counter
The counter overflow interrupt request or remote control interrupt request
INT2 interrupt input
Noise filter Interrupt interval determination register address 003016
Noise filter sampling clock selection bit 1/64 1/128 Divider
One-sided/both-sided detection selection bit 1/256 Data bus
f(XIN)
Fig. 35 Block diagram of interrupt interval datermination circuit
41
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
Interrupt interval determination control register (IIDCON : address 003116) Interrupt interval determination circuit operating selection bit 0 : Stopped 1 : Operating Counter sampling clock selection bit 0 : f(XIN)/256 1 : f(XIN)/512 Noise filter sampling clock selection bits(INT2) 0 0 : Filter stop 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256 One-sided/both-sided edge detection selection bit 0 : One-sided edge detection 1 : Both-sided edge detection Not used (return "0" when read)
Fig. 36 Structure of interrupt interval determination control register
(When IIDCON4 = "0") Noise filter Sampling clock
INT2 pin
Acceptance of interrupt
Counter sampling clock N 8-bit binary up counter value 0 1 2 3 4 5 FE 0 6 Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 6 Remote control interrupt request 1 2 3 0 3 3 Counter overflow interrupt request 1 FF FF FF
6
0
Fig. 37 Interrupt interval determination operation example (at rising edge active)
42
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(When IIDCON4 = "1") Noise filter Sampling clock
INT2 pin
Acceptance of interrupt Counter sampling clock N 8-bit binary up counter value N Interrupt interval determination register value N Remote control interrupt request Remote control interrupt request 0 1 1 1 Remote control interrupt request 0 1 2 3 FE 4 0 4 4 Remote control interrupt request 1 1 1 Remote control interrupt request 0 1 1 1 Remote control interrupt request 0 1 1 1 0 FF FF Counter overflow interrupt request 0 FF
Fig. 38 Interrupt interval determination operation example (at both-sided edge active)
43
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ZERO CROSS DETECTION CIRCUIT
The zero cross detection circuit compares the voltage applied to P45/INT1/ZCR pin and VSS. The result can be read from the zero cross detection circuit input bit (bit 7) of the zero cross detection control register. It is set to "1" when the input voltage is higher than VSS and to "0" when it is lower than VSS. The input signal to P45/ INT1/ZCR pin can select to either pass through the zero cross detection comparator or not to do. When using 100 V AC as input signal, insert an external circuit between it and P45/INT1/ZCR pin. Set the input current limiting resistors used in the external circuit to a value which satisfies the absolute maximum rating of port P45.
VCC 100V AC R1 R2 P45/INT1/ZCR
VSS
Fig. 39 External circuit example for zero cross detection
b7
b0
Zero cross detection control register (ZCRCON : address 003916) Zero cross detection ON/OFF selection bit 0 : Without passing through zero cross detection comparator 1 : Passing through zero cross detection comparator Not used (returns "0" when read) Noise filter sampling clock selection bits (INT1) b3 b2 0 0 : Not use noise filter 0 1 : f(XIN)/64 or f(XCIN)/64 1 0 : f(XIN)/128 or f(XCIN)/128 1 1 : f(XIN)/256 or f(XCIN)/256 One-sided/both-sided edge detection selection bit 0 : One-sided edge detection 1 : Both-sided edge detection Not used (return "0" when read) Zero cross detection circuit input bit (read only) 0 : Less than 0 V 1 : 0 V or more
Fig. 40 Structure of zero cross detection control register
P45/INT1/ZCR Zero cross detection ON/OFF selection bit "0" "1" Rising/falling edge switch When not using the filter When using the filter INT1/ZCR interrupt request
Zero cross detection circuit input bit Zero cross detection comparator
Noise filter
One-sided/both-sided edge detection selection bit Noise filter sampling clock selection bit f(XCIN) f(XIN)
1/256 1/28 1/64 Divider
Fig. 41 Block diagram of zero cross detection circuit
44
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOISE FILTER
The noise filter uses a sampling clock to remove the noise component digitally from the input signal of P45/INT1/ZCR pin. The sampling clock can be selected from 8 s, 16 s, or 32 s (at f(XIN)= 8.38 MHz) and this is used to change the noise component to be removed. It is also possible to generate an internal trigger and INT1/ZCR interrupt request directly without passing through
the noise filter. When passing through the noise filter, either bothsided edge detection or one-sided edge detection can be selected as the interrupt request generating source. The zero cross detection control register is used for this selection. Furthermore, switch between rising edge and falling edge is performed with the bit 1 of the interrupt edge selection register (address 003A16).
Input signal from P45/INT1/ZCR pin
D C R
Q
A
D C R
Q
B
S R
Q
C
D C R
Q
One-sided/both-sided edge detection selection bit (bit 4 of ZCRCON) "0" INT1/ZCR "1" interrupt request
Sampling clock
RESET
Fig. 42 Noise filter circuit diagram
RESET Sampling clock P45/INT1/ZCR Input signal from P45/INT1/ZCR pin A B C (one-sided edge) (both-sided edge) (Note 2) Switched with bit 4 of ZCRCON (Note 1) 0V
INT1/ZCR interrupt request
Notes 1 2
: Ignored this because of treating this as noise : INT1/ZCR interrupt request occurs
Fig. 43 Timing of noise filter circuit
45
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L" level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.8 V and 5.5 V, and XIN oscillation is stable), reset is released. In order to give the XIN clock time to stabilize, internal operation does not begin until after about 4000 XIN clock cycles (256 cycles of f(XIN)/16) are completed. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order) and address FFFC16 (low-order). Make sure that the reset input voltage is 0.5 V or less for 2.8 V of VCC.
Poweron Power source voltage RESET VCC 0V Reset input voltage 0.2VCC 0V Note : Reset release voltage : VCC = 2.8 V (Note)
RESET
VCC Power source voltage detection circuit
Fig. 44 Example of reset circuit
XIN RESET Internal reset
Address
?
?
?
?
FFFC
FFFD
ADH, ADL Reset address from vector table
Data SYNC about 4000 XIN clock cycles
?
?
?
?
ADL
ADH
Notes 1 : f(XIN) and f() are in the relationship : f(XIN) = 8*f() 2 : A question mark (?) indicates an undefined state that depends on the previous state.
Fig. 45 Reset sequence
46
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address (1) Port P0 (2) Port P1 (3) Port P2 (4) Port P2 direction register (5) Port P3 (6) Port P4 (7) Port P4 direction register (8) Port P5 (9) Port P5 direction register (10) Port P6 (11) Port P6 direction register (12) Port P7 (13) Port P7 direction register (14) Port P8 (15) Port P8 direction register (16) Port P9 (17) Port PA (18) Port PA direction register (19) Port PB (20) Port PB direction register (21) Serial I/O1 control register (22) Serial I/O automatic transfer control register (23) Serial I/O automatic transfer interval register (24) Serial I/O2 control register (25) Serial I/O3 control register (26) Timer 1 (27) Timer 2 (28) Timer 3 (29) Timer 4 (30) Timer 5 (001D16) * * * (001E16) * * * (002016) * * * (002116) * * * (002216) * * * (002316) * * * (002416) * * * (001C16) * * * (000016) * * * (000216) * * * (000416) * * * (000516) * * * (000616) * * * (000816) * * * (000916) * * * (000A16) * * * (000B16) * * * (000C16) * * * (000D16) * * * (000E16) * * * (000F16) * * * (001016) * * * (001116) * * * (001216) * * * (001416) * * * (001516) * * * (001616) * * * (001716) * * * (001916) * * * (001A16) * * *
Register contents 0016 0016 0016 0F16 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (31) Timer 6 (32) Timer 12 mode register (33) Timer 34 mode register (34) Timer 56 mode register (35) D-A conversion register (36) AD/DA control register (37) Interrupt interval determination control register (38) Port P0 segment/digit switch register (39) Port P2 digit/port switching register (40) Port P8 segment/port switch register (41) Port PA segment/port switch (42) FLDC mode register 1 (43) FLDC mode register 2 (44) Zero cross detection control register (45) Interrupt edge selection register (46) CPU mode register (47) Interrupt request register 1 (48) Interrupt request register 2 0016 (49) Interrupt control register 1 (50) Interrupt control register 2 0016 0016 FF16 0116 FF16 FF16 FF16 (51) Processor status register (52) Program counter
Address (002516) * * * (002816) * * * (002916) * * * (002A16) * * * (002B16) * * * (002C16) * * * (003116) * * *
Register contents FF16 0016 0016 0016 0016 1016 0016
(003216) * * *
0016
(003316) * * *
0016
(003416) * * *
0016
(003516) * * * (003616) * * * (003716) * * * (003916) * * *
0016 0016 0016 0016
(003A16) * * *
0016
(003B16) * * * 0 1 0 0 1 0 0 0 (003C16) * * * (003D16) * * * (003E16) * * * (003F16) * * * 0016 0016 0016 0016
(PS) * * * ! ! ! ! ! 1 ! ! (PCH) * * * Contents of address FFFD16 (PCL) * * * Contents of address FFFC16
Note : ! : Undefined The contents of all other registers and RAM are undefined at reset, so set their initial values.
Fig. 46 Internal status at reset
47
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
The 3819 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after poweron, only the XIN oscillation circuit starts oscillation, and XCIN and XCOUT pins function as I/O ports.
Oscillation Control
Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116". Either XIN or XCIN divided by 16 is input to timer 1, and the output of timer 1 is connected to timer 2. The bits of the timer 12 mode register are cleared to "0". Set the timer 1 and timer 2 interrupt enable bits to disabled ("0") before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is received, but the internal clock is not supplied to the CPU until timer 1 underflows. When using an external resonator, it is necessary for oscillating to stabilize. Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.
Frequency Control
Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected. High-speed mode The internal clock is half the frequency of XIN. Low-speed mode The internal clock is half the frequency of XCIN.
Note : If you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the XCIN oscillation to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3*f(XCIN).
Low-power dissipation mode When stopping the main clock XIN in the low-speed mode, the lowpower dissipation operation starts. To stop the main clock, set the bit 5 of the CPU mode register to "1". When the main clock XIN is restarted, set enough time for oscillation to stabilize by programming. The low-power dissipation operation 200 A or less (at f(XIN) = 32 kHz) can be realized by reducing the XCIN-XCOUT drivability. To reduce the XCIN-XCOUT drivability, clear the bit 3 of the CPU mode register to "0". At reset or when executing the STP instruction, this bit is set to "1" and strong drivability is selected to help the oscillation to start.
XCIN
XCOUT Rf
XIN
XOUT
Rd CCOUT CIN COUT
CCIN
Fig. 47 Ceramic resonator external circuit
XCIN
XCOUT Open
XIN
XOUT Open
External oscillation circuit or pulse VCC VSS VCC VSS
External oscillation circuit
Fig. 48 External clock input circuit
48
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
XCOUT "1" "0" Port XC switch bit (Note 3)
XIN
Internal system clock selection bit (Note 1, 3) Low-speed mode "1" 1/2 1/4 1/2 "0" Middle/ High-speed mode XOUT
Timer 1 count source selection bit (Note 2) "1" Timer 1 "0"
Main clock division ratio selection bit (Note 3) Middle-speed mode High-speed mode or Low-speed mode Main clock stop bit (Note 3) Timing (Internal clock)
Q
S R STP instruction WIT instruction
S R
Q
Q
S R STP instruction
Reset Interrupt disable flag I Interrupt request Notes 1 : When selecting the low-speed mode, set the port XC switch bit to "1". 2 : Refer to the structure of timer 12 mode register. 3 : Refer to the structure of CPU mode register (next page).
Fig. 49 Clock generating circuit block diagram
49
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
Middle-speed mode ( =1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (XIN oscillating) CM4 = 0 (32 kHz stopped)
CM6 "1" "0"
High-speed mode ( = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (XIN oscillating) CM4 = 0 (32 kHz stopped)
"0"
4 " CM "0 " 6 "1 CM "0" " "1
CM4
"1"
6
"0
"
High-speed mode ( = 4 MHz) CM7 = 0 (8 MHz selected) CM6 = 0 (High-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32 kHz oscillating)
Middle-speed mode ( =1 MHz) CM7 = 0 (8 MHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32 kHz oscillating)
CM6 "1" "0"
"0"
CM7
"1"
CM7 CM6 "1" "0" Low-speed mode ( = 16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32 kHz oscillating) "1"
Low-speed mode ( =16 kHz) CM7 = 1 (32 kHz selected) CM6 = 1 (Middle-speed) CM5 = 0 (XIN oscillating) CM4 = 1 (32 kHz oscillating)
"0"
"1"
"1
"
CM
"1
"
CM4
"0
"
CM
4
"0"
b7
b0
CPU mode register (CPUM (CM) : address 003B 16)
CM5
"1"
6
"1
"
"0
"
Low power dissipation mode ( =16 kHz) CM6 CM7 = 1 (32 kHz selected) "1" "0" CM6 = 1 (Middle-speed) CM5 = 1 (XIN stopped) CM4 = 1 (32 kHz oscillating)
Low power dissipation mode ( =16 kHz) CM7 = 1 (32 kHz selected) CM6 = 0 (High-speed) CM5 = 1 (XIN stopped) CM4 = 1 (32 kHz oscillating)
Notes 1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. Timer operates in the wait mode. 3 : When the stop mode is released in middle/high-speed mode, a delay of approximately 0.5 ms occurs automatically by timer 1. 4 : When the stop mode is released in low-speed mode, a delay of approximately 0.125 s occurs automatically by timer 1. 5 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal clock.
Fig. 50 State transitions of system clock
50
"1"
"1
"
CM
6
"
0"
"1
"
CM
"1
"
CM5
CM
5
" "0
"0
"
CM
5
CM4 : Port XC switch bit 0 : I/O port function 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN-XOUT) stop bit 0 : Oscillating 1 : Stopped CM6 : Main clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) CM7 : Internal system clock selection bit 0 : XIN-XOUT selected (middle/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
"0"
"0"
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING Processor Status Register
The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1". After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations.
Serial I/O
When using an external clock, input "H" to the external clock input pin and clear the serial I/O interrupt request bit before executing serial I/O transfer and serial I/O automatic transfer. When using the internal clock, set the synchronous clock to internal clock, then clear the serial I/O interrupt request bit before executing a serial I/O transfer and serial I/O automatic transfer.
Interrupts
The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(XIN) is 500 kHz or more during an A-D conversion. Do not execute the STP or WIT instruction during an A-D conversion.
Decimal Calculations
* To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. * In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flag are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC.
Instruction Execution Time
The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN or XCIN frequency.
At the STP Instruction Release
At the STP instruction release, all bits of the timer 12 mode register are cleared. The XCOUT drivability selection bit (the CPU mode register) is set to "1" (high drive) in order to start oscillating.
Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
Multiplication and Division Instructions
* The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. * The execution of these instructions does not change the contents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The following cannot be used: * the data transfer instruction (LDA, etc.) * the operation instruction when the index X mode flag (T) is "1" * the addressing mode which uses the value of a direction register as an index * the bit-test instruction (BBC or BBS, etc.) to a direction register * the read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers.
51
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies)
PROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and builtin EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter.
Package 100P6S-A 100D0
Name of Programming Adapter PCA4738F-100A PCA4738L-100A
Set the address of PROM programmer in the user ROM area. The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after writing, the procedure shown in Figure 51 is recommended to verify programming.
Programming with PROM Programmer
Screening (Caution) (150C for 40 hours)
Verification with PROM Programmer
Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150C exceeding 100 hours.
Fig. 51 Programming and testing of One Time PROM version
52
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VEE VI VI VI VI VI VO Parameter Power source voltage Pull-down power source voltage Input voltage P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, PB0-PB3 Input voltage P40, P45 Input voltage P80-P87, PA0-PA7 All voltages are based on VSS. Input voltage RESET, XIN Output transistors are cut off. Input voltage XCIN Output voltage P00-P07, P10-P17, P20-P23, P30-P37, P80-P87, P90-P97, PA0-PA7 Output voltage P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, PB0-PB3, XOUT, XCOUT Ta = 25C Power dissipation Operating temperature Storage temperature Conditions Ratings -0.3 to 7.0 VCC -40 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 VCC -40 to VCC +0.3 -0.3 to VCC +0.3 -0.3 to VCC +0.3 VCC -40 to VCC +0.3 Unit V V V V V V V V
VO Pd Topr Tstg
-0.3 to VCC +0.3 600 -10 to 85 -40 to 125
V mW C C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VSS VEE VREF AVSS VIA VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL Power source voltage Parameter High-speed mode Middle/Low-speed mode
(Vcc = 4.0 to 5.5 V, Ta = -10 to 85C, unless otherwise noted) Min. 4.0 2.8 VCC-38 2.0 3.0 0 0 0.75VCC 0.4VCC 0.8VCC 0.8VCC 0.8VCC 0 0 0 0 0 VCC VCC VCC VCC VCC VCC 0.25VCC 0.16VCC 0.2VCC 0.2VCC 0.2VCC Limits Typ. 5.0 5.0 0 Max. 5.5 5.5 VCC VCC VCC Unit V V V V V V V V V V V V V V V V V V
Power source voltage Pull-down power source voltage Analog reference voltage (when using A-D converter) Analog reference voltage (when using D-A converter) Analog power source voltage Analog input voltage AN0-AN15 "H" input voltage P40-P47, P50-P57, P60-P67, P70-P77, PB0-PB3 "H" input voltage P24-P27 "H" input voltage P80-P87, PA0-PA7 "H" input voltage RESET "H" input voltage XIN, XCIN "L" input voltage P40-P47, P50-P57, P60-P67, P70-P77, PB0-PB3 "L" input voltage "L" input voltage "L" input voltage "L" input voltage P24-P27 P80-P87, PA0-PA7 RESET XIN, XCIN
53
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
(Vcc = 4.0 to 5.5 V, Ta = -10 to 85C, unless otherwise noted) Limits Min. Typ. Max. -240 Unit
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg) f(CNTR0) f(CNTR1) f(XIN) f(XCIN)
"H" total peak output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87, P90-P97, (Note 1) PA6, PA7 "H" total peak output current P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, PA0-PA5, (Note 1) PB0-PB3 "L" total peak output current P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, (Note 1) PB0-PB3 "H" total average output current P00-P07, P10-P17, P20-P27, P30-P37, P80-P87, P90-P97, (Note 1) PA6, PA7 "H" total average output current P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, PA0-PA5, (Note 1) PB0-PB3 "L" total average output current P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, (Note 1) PB0-PB3 "H" peak output current P00-P07, P10-P17, P20-P23, P30-P37, P80-P87, P90-P97, (Note 2) PA0-PA7 "H" peak output current P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, (Note 2) PB0-PB3 "L" peak output current P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, (Note 3) PB0-PB3 "H" average output current P00-P07, P10-P17, P20-P23, P30-P37, P80-P87, P90-P97, (Note 3) PA0-PA7 "H" average output current P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, (Note 3) PB0-PB3 "L" average output current P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, (Note 3) PB0-PB3 Clock input frequency for timers 2 and 4 (duty cycle 50%) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5)
mA
-60
mA
100
mA
-120
mA
-30
mA
50
mA
-40
mA
-10
mA
10
mA
-18
mA
-5.0
mA
5.0 250 8.4 50
mA kHz MHz kHz
32.768
Notes 1 : The total output current is the sum of all the currents flowing through all the applicable ports.The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2 : The peak output current is the peak current flowing in each port. 3 : The average output current in an average value measured over 100 ms. 4 : When the oscillation frequency has a 50% duty cycle. 5 : When using the microcomputer in low-speed operation mode, set the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
54
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
Symbol Parameter
(Vcc = 4.0 to 5.5 V, Ta = -10 to 85C, unless otherwise noted) Limits Test conditions Min. VCC-2.0 Typ. Max. Unit
VOH
VOH
VOL
"H" output voltage P00-P07, P10-P17, P20-P23, P30-P37, P80-P87, P90-P97, PA0-PA7 "H" output voltage P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, PB0-PB3 "L" output voltage P24-P27, P41-P44, P46, P47, P50-P57, P60-P67, P70-P77, PB0-PB3 Hysteresis INT0-INT4, SIN1, SIN2, SIN3, SCLK11, SCLK2, SCLK3, CS, CNTR0, CNTR1 Hysteresis RESET, XIN Hysteresis XCIN "H" input current P24-P27, P40-P47, P50-P57, P60-P67, P70-P77, PB0-PB3 "H" input current P80-P87, PA0-PA7 (Note) "H" input current RESET, XCIN "H" input current XIN "L" input current P24-P27, P40-P47, P50-P57, P60-P67, P70-P77, PB0-PB3 "L" input current P80-P87, PA0-PA7 (Note) "L" input current RESET, XCIN "L" input current XIN Output load current P00-P07, P10-P17, P20-P23, P30-P37, P90-P97 Output leakage current P00-P07, P10-P17, P20-P23, P30-P37, P80-P87, P90-P97, PA0-PA7 RAM hold voltage
IOH=-18 mA
V
IOH=-10 mA
VCC-2.0
V
IOL=10 mA When using a non-port function
2.0
V
VT+-VT- VT+-VT- VT+-VT- IH IH IH IH IL IL IL IL ILOAD
0.4 0.5 0.5
V V V 5.0 5.0 5.0 A A A A A A A A A
VI=VCC VI=VCC VI=VCC VI=VCC VI=VSS VI=VSS VI=VSS VI=VSS VEE=VCC-36 V, VOL=VCC, Output transistors "off" VEE=VCC-38 V, VOL=VCC-38 V, Output transistors "off" When clock is stopped 2
4.0 -5.0 -5.0 -5.0 -4.0 150 500 900
ILEAK
-10
A
VRAM
5.5
V
Note : Except when reading ports P8 or PA.
55
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (VCC = 4.0 to 5.5 V, Ta = -10 to 85C, unless otherwise noted)
Symbol Parameter Test conditions * High-speed mode f(XIN) = 8.4 MHz f(XCIN) = 32 kHz Output transistors "off" * High-speed mode f(XIN) = 8.4 MHz (in WIT state) f(XCIN) = 32 kHz Output transistors "off" * Middle-speed mode f(XIN) = 8.4 MHz f(XCIN) = stopped Output transistors "off" * Middle-speed mode f(XIN) = 8.4 MHz (in WIT state) f(XCIN) = stopped Output transistors "off" * Low-speed mode f(XIN) = stopped, f(XCIN) = 32 kHz Low-power dissipation mode set (CM3) = 0 Output transistors "off" * Low-speed mode f(XIN) = stopped f(XCIN) = 32 kHz (in WIT state) Low-power dissipation mode set (CM3) = 0 Output transistors "off" Increase at A-D converter operating f(XIN) = 8.4 MHz Increase at zero cross detection (P45 = VCC) All oscillation stopped Ta = 25C (in STP state) Output transistors "off" Ta = 85C 60 200 A Min. Limits Typ. Max. Unit
7.5
15
mA
1
mA
3
mA
1
mA
ICC
Power source current
20
40
A
0.6 1 0.1 1 10
mA mA A
56
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ZERO CROSS DETECTION INPUT CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -10 to 85C, unless otherwise noted) Symbol fZCR VT Parameter Input frequency of zero cross detection Voltage error of zero cross detection distinction Test conditions Limits Min. -100 Typ. 50, 60 0 Max. 1000 100 Unit Hz mV
50 Hz or 60 Hz
1/fZCR
100V AC
P45/INT1/ZCR clamp correction input waveform
5.7 V VT VI 0V - 0.7 V
Zero cross detection comparator output
Fig. 52 Zero cross detection input characteristics
A-D CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -10 to 85C, high-speed operation mode f(XIN) = 500 kHz to 8.4 MHz, unless otherwise noted) Symbol - - TCONV IVREF IIA RLADDER Parameter Resolution Absolute accuracy (excluding quantization error) Conversion time Reference power source input current Analog port input current Ladder resistor Test conditions Limits Min. Typ. 1 49 50 150 0.5 35 Max. 8 2.5 50 200 5.0 Unit Bits LSB tc () A A k
VCC = VREF = 5.12 V VREF = 5 V
D-A CONVERTER CHARACTERISTICS
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 to VCC, Ta = -10 to 85C, unless otherwise noted) Symbol - - Tsu RO IVREF Resolution Absolute accuracy VCC = 4.0 to 5.5 V VCC = 3.0 to 5.5 V 1 2.5 Parameter Test conditions Limits Min. Typ. Max. 8 1.0 2.5 3 4 3.2 Unit Bits % % s k mA
Setting time Output resistor Reference power source input current (Note)
Note : Exclude currents flowing through the A-D converter ladder resistor
57
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -10 to 85C, unless otherwise noted)
Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(XcIN) tWH(XcIN) tWL(XcIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(SCLK-SIN) th(SCLK-SIN) Parameter Reset input "L" pulse width Main clock input cycle time (XIN input) Main clock input "H" pulse width Main clock input "L" pulse width Sub-clock input cycle time (XCIN input) Sub-clock input "H" pulse width Sub-clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0-INT4 input "H" pulse width INT0-INT4 input "L" pulse width Serial I/O clock input cycle time Serial I/O clock input "H" pulse width Serial I/O clock input "L" pulse width Serial I/O input setup time Serial I/O input hold time Limits Min. 2.0 119 30 30 20 5.0 5.0 4.0 1.6 1.6 80 80 1.0 400 400 200 200 Typ. Max. Unit s ns ns ns s s s s s s ns ns s ns ns ns ns
SWITCHING CHARACTERISTICS (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -10 to 85C, unless otherwise noted)
Symbol tWH(SCLK) tWL(SCLK) td(SCLK-SOUT) tv(SCLK-SOUT) tr(SCLK) tf(SCLK) tr(Pch-strg) tf(Pch-weak) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time Serial I/O output hold time Serial I/O clock output rising time Serial I/O clock output falling time High-breakdown-voltage P-channel opendrain output rising time (Note 1) High-breakdown-voltage P-channel opendrain output falling time (Note 2) Test conditions CL = 100 pF CL = 100 pF Limits Min. tc(SCLK) /2-160 tc(SCLK) /2-160 0.2tc(SCLK) 0 CL = 100 pF CL = 100 pF CL = 100 pF VEE = VCC -36 V CL = 100 pF VEE = VCC -36 V 55 1.8 40 40 Typ. Max. Unit ns ns ns ns ns ns ns s
Notes 1 : When the bit 7 of the FLDC mode register 1 (address 003616) is at "0". 2 : When the bit 7 of the FLDC mode register 1 (address 003616) is at "1".
Serial clock output port
P56/SCLK3, P52/SCLK2, P66/SCLK11 CL
High-breakdown-voltage P-channel open-drain output port
P0, P1, P20-P23, P3, P8, P9, PA CL
(Note) Note : Ports P8 and PA need external resistors.
VEE
Fig. 53 Circuit for measuring output switching characteristics
58
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGRAM
tC(CNTR)
tWH(CNTR) tWL(CNTR)
CNTR0 CNTR1
0.8VCC 0.2VCC
tWH(INT)
tWL(INT)
0.8VCC
INT0INT4
0.2VCC
tW(RESET)
RESET
0.2VCC
0.8VCC
tC(XIN) tWH(XIN) tWL(XIN)
XIN
0.8VCC
0.2VCC
tC(XCIN) tWH(XCIN) tWL(XCIN)
XCIN
0.8VCC
0.2VCC
tC(SCLK)
t
f
tWL(SCLK)
0.2VCC
t
r
tWH(SCLK)
SCLK
0.8VCC
tsu(SIN-SCLK)
0.8VCC
th(SCLK-SIN)
SIN
0.2VCC
td(SCLK-SOUT)
tv(SCLK-SOUT)
SOUT
59
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Power source current characteristic examples
Figures 54 and 55 show power source current characteristic examples. [Measuring condition : 25 C, f(XCIN) = 32 kHz, A-D conversion operating, in high-speed mode]
Power source current (mA) 10 at 5.0 V 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8.4 8 9 10 Frequency f(XIN)(MHz)
Rectangular waveform
Fig. 54 Power source current characteristic example
[Measuring condition : 25 C, f(XCIN) = 32 kHz, A-D conversion operating, in high-speed mode]
Power source current (mA) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 5 6 7 8.4 8 9 10 Frequency f(XIN)(MHz)
Rectangular waveform
at 5.0 V
Fig. 55 Power source current characteristic example (in wait mode)
60
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port standard characteristic examples
Figures 56, 57, and 58 show port standard characteristic examples. [Port P87 IOH-VOH characteristic] (Pins with same characteristic : P0, P1, P20-P23, P3, P8, P9, PA)
IOH (mA) -100 Vcc = 5.0 V 90 C Vcc = 5.5 V 25 C
-80 Vcc = 3.0 V 25 C -60 Vcc = 5.0 V 25 C Vcc = 5.5 V 90 C
-40
Vcc = 3.0 V 90 C
-20
0 0 1 2 3 4 5 6 VOH (V)
Fig. 56 Standard characteristic example of High-breakdown-voltage P-channel open-drain output port
[Port P77 IOH-VOH characteristic (P-channel drive)] (Pins with same characteristic : P24-P27, P41-P44, P46, 47, P5, P6, P7, PB)
IOH (mA) -50 Vcc = 5.5V 25 C
-40 Vcc = 5.0V 90 C
-30
Vcc = 5.5V 90 C
-20
Vcc = 3.0V 25 C
Vcc = 5.0V 25 C
-10 Vcc = 3.0V 90 C 0 0 1 2 3 4 5 6
VOH (V)
Fig. 57 Standard characteristic example of CMOS output port at P-channel drive
61
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Port P77 IOL-VOL characteristic (N-channel drive)] (Pins with same characteristic : P24-P27, P41-P44, P46, 47, P5, P6, P7, PB)
IOL (mA) 50 Vcc = 5.0 V 25 C Vcc = 5.5 V 90 C Vcc = 5.0 V 90 C
Vcc = 5.5 V 25 C
40
30 Vcc = 3.0 V 25 C Vcc = 3.0 V 90 C 10
20
0
0
1
2
3
4
5
6 VOL (V)
Fig. 58 Standard characteristic example of CMOS output port at N-channel drive
62
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D conversion standard characteristics
Figure 59 shows the A-D conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. It represents the deviation from the ideal value. For example, the conversion of output code from 0016 to 0116 occurs ideally at the point of AN0 = 10 mV, but the measured value is -4 mV. Accordingly, the measured point of conversion is represented as "10 - 4 = 6 mV". The upper-side line on the graph indicates the width of input voltages equivalent to output codes. For example, the measured width of the input voltage for output code 4916 is 23 mV, so the differential nonlinear error is represented as "23 - 20 = 3 mV" (0.1 LSB).
M38197MA-000FP A-D CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the high-speed mode Fig. 59 A-D conversion standard characteristics
63
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A conversion standard characteristics
Figure 60 shows the D-A conversion standard characteristics. The lower-side line on the graph indicates the absolute precision error. In this case, it represents the difference between the ideal analog output value for an input code and the measured value. The upper-side line on the graph indicates the change width of output analog value to a one-bit change of input code.
M38197EAFP D-A CONVERTER STEP WIDTH MEASUREMENT
Measured when a power source voltage is stable in the high-speed mode Fig. 60 D-A conversion standard characteristics
64
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Functional description supplement
Interrupt 3819 group permits interrupts on the basis of 20 sources. It is vector interrupts with a fixed priority system. Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority interrupt is accepted first. This priority is determined by hardware, but variety of priority processing can be performed by software, using an interrupt enable bit and an interrupt disable flag. For interrupt sources, vector addresses and interrupt priority, refer to "Table 5." Table 5. Interrupt sources, vector addresses and interrupt priority Priority 1 2 3 Interrupt sources Reset (Note) INT0 interrupt INT1/ZCR interrupt INT2 interrupt 4 Remote control/counter overflow interrupt Serial I/O 1 interrupt Serial I/O 1 automatic transfer interrupt Serial I/O 2 interrupt Serial I/O 3 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt Timer 5 interrupt Timer 6 interrupt INT3 interrupt INT4 interrupt 15 A-D conversion interrupt FLD blanking interrupt 16 17 FLD digit interrupt BRK instruction interrupt FFDD16 FFDC16 FFDF16 FFDE16 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 Vector addresses
High-order Low-order
Remarks Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when interrupt interval determination operates Valid when serial I/O ordinary mode is selected Valid when serial I/O automatic transfer mode is selected Valid when serial I/O 2 is selected Valid when serial I/O 3 is selected STP release timer underflow
FFFD16 FFFB16 FFF916 FFF716
FFFC16 FFFA16 FFF816 FFF616
FFF516
FFF416
5 6 7 8 9 10 11 12 13 14
External interrupt (active edge selectable) Valid when INT4 interrupt is selected External interrupt (active edge selectable) Valid when A-D converter interrupt is selected Valid when FLD blanking interrupt is selected Valid when FLD digit interrupt is selected Non-maskable software interrupt
Note : Reset functions in the same way as an interrupt with the highest priority.
65
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timing after interrupt The interrupt processing routine begins with the machine cycle following the completion of the instruction that is currently in execution. Figure 61 shows a timing chart after an interrupt occurs, and figure 62 shows the time up to execution of the interrupt processing routine.
SYNC RD WR Address bus Data bus PC Not used
S, SPS S-1, SPS S-2, SPS
BL AL
BH
AL, AH AH
PCH
PCL
PS
SYNC : CPU operation code fetch cycle (This is an internal signal which cannot be observed from the external unit.) BL, BH : Vector address of each interrupt AL, AH : Jump destination address of each interrupt SPS : "0016" or "0116"
Fig. 61 Timing chart after an interrupt occurs
Generation of interrupt request
Start of interrupt processing
Main routine
Waiting time for post-processing of pipeline
Stack push and Vector fetch
Interrupt processing routine
0 to 16* cycles
2 cycles
5 cycles
7 to 23 cycles (At performing 8.4 MHz, 1.7 s to 5.5 s) * : at execution of DIV instruction
Fig. 62 Time up to execution of the interrupt processing routine
66
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D converter A-D conversion is started by setting A-D conversion completion bit to "0". During A-D conversion, internal operations are performed as follows. 1. After the start of A-D conversion, A-D conversion register goes to "0016." 2. The highest-order bit of A-D conversion register is set to "1", and the comparison voltage Vref is input to the comparator. Then, Vref is compared with analog input voltage VIN. 3. As a result of comparison, when Vref < VIN, the highest-order bit of A-D conversion register becomes "1." When Vref > VIN, the highest-order bit becomes "0." By repeating the above operations up to the lowest-order bit of the A-D conversion register, an analog value converts into a digital value. A-D conversion completes at 50 clock cycles (11.9 s at f(XIN) = 8.4 MHz) after it is started, and the result of the conversion is stored into the A-D conversion register. Concurrently with the completion of A-D conversion, A-D conversion interrupt request occurs, so that the A-D conversion interrupt request bit is set to "1".
Relative formula for a reference voltage VREF of A-D converter and Vref When n = 0 Vref = 0 VREF When n = 1 to 255 Vref = ! (n-0.5) 256 n : the value of A-D converter (decimal numeral) Table 6. Change of A-D conversion register during A-D conversion Change of A-D conversion register At start of conversion First comparison Second comparison Third comparison After completion of eighth comparison 0 1 *1 *1 0 0 1 *2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VREF 2 VREF 2 VREF 2 - VREF 512 VREF 4 VREF 4 Value of comparison voltage (Vref) 0
-
VREF 512 VREF 8
-
VREF 512
A result of A-D conversion *1 *2 *3 *4 *5 *6 *7 *8
*1 : A result of the first comparison *3 : A result of the third comparison *5 : A result of the fifth comparison *7 : A result of the seventh comparison
*2 : A result of the second comparison *4 : A result of the fourth comparison *6 : A result of the sixth comparison *8 : A result of the eighth comparison
67
MITSUBISHI MICROCOMPUTERS
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Figures 63 shows A-D conversion equivalent circuit, and figure 64 shows A-D conversion timing chart.
VCC about 2 k AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
VSS VIN Sampling clock
VCC AVSS
C Chopper amplifier
A-D conversion register
b3 b2 b1 b0
A-D control register VREF
Build-in D-A converter
A-D conversion interrupt request Vref
Reference clock
AVSS
Fig. 63 A-D conversion equivalent circuit
Write signal for AD/DA control register
50 cycles
A-D conversion completion flag
Sampling clock
Fig. 64 A-D conversion timing chart
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2.1 I/O port 2.2 Timer 2.3 Serial I/O 2.4 A-D conversion 2.5 FLD controller 2.6 Interrupt interval determination function 2.7 Zero cross detection circuit 2.8 Reset 2.9 Clock generating circuit
MITSUBISHI MICROCOMPUTER
2. APPLICATION
2.1 I/O Port
2.1.1 Related registers
3819 Group 2.1 I/O port
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi) (i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B) [Address:00 16, 0216, 0416, 0616, 0816, 0A16, 0C16, 0E16, 1016, 1216, 1416, 1616]
B 0 Port Pi0 1 Port Pi1
Name
q
Function
In output mode Write Port latch Read In input mode Write : Port latch Read : Value of pins (Note)
At reset
RW
0 0 0 0 0 0 0 0
q
2 Port Pi2 3 Port Pi3 4 Port Pi4 5 Port Pi5 6 Port Pi6 7 Port Pi7
Note : Port PB register [Address:16 16] Port PB is a four-bit port (PB 0 to PB3). Accordingly, when bits 4 to 7 are read out, the contents are "0."
Fig. 2.1.1 Structure of Port Pi (i = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)
Port P2 direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port P2 direction register (P2D) [Address:0516]
B Name Function 0 Because P20 to P23 are output ports, these bits do not have a 1 direction register function and nothing is allocated. 2 3 0 : Port P24 input mode 4 Port P2 direction register
1 : Port P24 output mode 0 : Port P25 input mode 1 : Port P25 output mode 0 : Port P26 input mode 1 : Port P26 output mode 0 : Port P27 input mode 1 : Port P27 output mode
At reset
RW
! ! ! ! ! ! ! ! ! ! ! !
1 1 1 1 0 0 0 0
5 6 7
Fig. 2.1.2 Structure of Port P2 direction register
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3819 Group 2.1 I/O port
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD) (i = 4, 5, 6, 7, 8, A, B) [Address:09 16, 0B16, 0D16, 0F16, 1116, 1516, 1716]
B
Name
Function
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode (Note)
At reset
RW
! ! ! ! ! ! ! !
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0
(Note)
0 0 0
Note : Port P4 direction register [Address:09 16] Ports P40 and P45 are input ports. Accordingly, these bits do not have a direction register function.
Fig. 2.1.3 Structure of Port Pi direction register (i = 4, 5, 6, 7, 8, A, B)
2.1.2 Handling of unused pins Table 2.1.1 Handling of unused pins Name of Pins/Ports P0, P1, P20-P23, P3, P9 P24-P27, P41-P44, P46, P47, P5, P6, P7, P8, PA, PB P40 P45 VEE, AVSS VREF Open * Set to the input mode and connect to VCC or VSS through each resistor. * Set to the output mode and open at "L" or "H." Connect to VSS(GND) through the resistor. Connect to VCC through the resistor. Connect to VSS(GND). Connect to VSS(GND) through the resistor. Handling
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2.2 Timer
2.2.1 Related registers
Timer i
b7 b6 b5 b4 b3 b2 b1 b0 Timer i (Ti) (i = 1, 3, 4, 5, 6) [Address:20 16, 2216, 2316, 2416, 2516]
3819 Group 2.2 Timer
B 0 1 2 3 4 5 6 7
Function
q q q
At reset
RW
The count value of the Timer i is set. The value set in this register is written to both the Timer i and the Timer i latch at the same time. When the Timer i is read out, the value (count value) of the Timer i is read out.
1 1 1 1 1 1 1 1
Fig. 2.2.1 Structure of Timer i (i = 1, 3, 4, 5, 6)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address:2116]
B 0 1 2 3 4 5 6 7
q q q
Function
The count value of the Timer 2 is set. The value set in this register is written to both the Timer 2 and the Timer 2 latch at the same time. When the Timer 2 is read out, the value (count value) of the Timer 2 is read out.
At reset
RW
1 0 0 0 0 0 0 0
Fig. 2.2.2 Structure of Timer 2
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3819 Group 2.2 Timer
Timer 6 PWM register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 6 PWM register (T6PWM) [Address:2716]
B 0 1 2 3 4 5 6 7
q q q
Function
In Timer 6 PWM mode Set the width of "L" of the PWM rectangular waveform. Duty of the PWM rectangular waveform : n/(n + m) Cycle : (n + m) ! ts n = a set value of the Timer 6 m = a set value of the Timer 6 PWM register ts = a cycle of the Timer 6 count source Selection of the Timer 6 PWM mode Set the Timer 6 operation mode selection bit of the Timer 56 mode register (Address : 2A 16) to "1".
At reset
RW
? ? ? ? ? ? ? ?
Fig. 2.2.3 Structure of Timer 6 PWM register
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 12 mode register (T12M) [Address:2816]
B
Name
Function
0 : Operating 1 : Stopped
At reset
RW
0 Timer 1 count stop bit 1 Timer 2 count stop bit
0 0 0 0 0 0 0 0
! !
0 : Operating 1 : Stopped 0 : f(XIN)/16 or f(XCIN)/16 2 Timer 1 count source 1 : f(XCIN) selection bit Nothing is allocated for this bit. It is a write disabled bit. 3 When this bit is read out, the value is "0. "
4 Timer 2 count source
selection bits
b5 b4
5 6 Timer 1 output selection bit
(P46) 7 Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0. "
00 : Timer 1 underflow 01 : f(XCIN) 10 : External count input CNTR 0 11 : Not available 0 : I/O port 1 : Timer 1 output
Fig. 2.2.4 Structure of Timer 12 mode register
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3819 Group 2.2 Timer
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address:2916]
B
Name
Function
0 : Operating 1 : Stopped 0 : Operating 1 : Stopped
At reset
RW
0 Timer 3 count stop bit 1 Timer 4 count stop bit 2 Timer 3 count source 3 4 5 6 7
0 0 0 0 0 0 0 0
! !
0 : f(XIN)/16 or f(XCIN)/16 1 : Timer 2 underflow selection bit Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0. " b5 b4 Timer 4 count source 00 : f(XIN)/16 or f(XCIN)/16 selection bits 01 : Timer 3 underflow 10 : External count input CNTR 1 11 : Not available 0 : I/O port Timer 3 output selection bit 1 : Timer 3 output (P47) Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0. "
Fig. 2.2.5 Structure of Timer 34 mode register
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Timer 56 mode register (T56M) [Address:2A16]
B
Name
Function
0 : Operating 1 : Stopped 0 : Operating 1 : Stopped 0 : f(XIN)/16 or f(XCIN)/16 1 : Timer 4 underflow 0 : Timer mode 1 : PWM mode
b5 b4
At reset
RW
0 Timer 5 count stop bit 1 Timer 6 count stop bit 2 Timer 5 count source
selection bit Timer 6 operation mode 3 selection bit 4 Timer 6 count source selection bits
0 0 0 0 0 0 0 0
5 6 Timer 6 (PWM)
output selection bit (P6 1) 7 Fix this bit to "0."
00 : f(XIN)/16 or f(XCIN)/16 01 : Timer 5 underflow 10 : Timer 4 underflow 11 : Not available 0 : I/O port 1 : Timer 6 output
Fig. 2.2.6 Structure of Timer 56 mode register
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Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address:3C16]
3819 Group 2.2 Timer
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T
0 INT0 interrupt request bit 1 INT1/ZCR interrupt request bit 2
q q
0 0 0
INT2 interrupt request bit Remote control/counter overflow interrupt request bit
3
Serial I/O 1 interrupt request bit q Serial I/O automatic transfer interrupt request bit
q
0
T
4 Serial I/O 2 interrupt request
bit 5 Serial I/O 3 interrupt request bit Timer 1 interrupt request bit 6
7 Timer 2 interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
0 0 0 0
T T T T
T "0" is set by software, but not "1."
Fig. 2.2.7 Structure of Interrupt request register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address:3D16]
b
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T
0 Timer 3 interrupt request bit 1 Timer 4 interrupt request bit 2 Timer 5 interrupt request bit 3 Timer 6 interrupt request bit 4 INT3 interrupt request bit 5
q q
0 0 0 0 0 0
INT4 interrupt request bit A-D conversion interrupt request bit
6
FLD blanking interrupt 0 : No interrupt request request bit 1 : Interrupt request q FLD digit interrupt request bit
q
0
T
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0." T "0" is set by software, but not "1."
0
T
Fig. 2.2.8 Structure of Interrupt request register 2
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3819 Group 2.2 Timer
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address:3E16]
b
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1/ZCR interrupt enable bit 2
q q
0 0 0
INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit
3
Serial I/O 1 interrupt enable bit q Serial I/O automatic transfer interrupt enable bit
q
0
4 Serial I/O 2 interrupt enable
bit Serial I/O 3 interrupt enable 5 bit 6 Timer 1 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
7 Timer 2 interrupt enable bit
Fig. 2.2.9 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address:3F16]
b
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 Timer 3 interrupt enable bit 1 Timer 4 interrupt enable bit 2 Timer 5 interrupt enable bit 3 Timer 6 interrupt enable bit 4 INT3 interrupt enable bit 5
q q
0 0 0 0 0 0
INT4 interrupt enable bit A-D conversion interrupt enable bit
6
FLD blanking interrupt enable bit q FLD digit interrupt enable bit
q
0 0
7 Fix this bit to "0."
Fig. 2.2.10 Structure of Interrupt control register 2
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2.2.2 Timer application examples (1) Basic functions and uses
3819 Group 2.2 Timer
[Function 1 ] Control of Event interval (Timers 1 to 6) The Timer count stop bit is set to "0" after setting a count value to a timer. Then a timer interrupt request occurs after a certain period. [Use ] * Generation of an output signal timing * Generation of a waiting time
[Function 2 ] Control of Cyclic operation : Generation of synchronous timing (Timers 1 to 6) The value of a timer latch is automatically written to a timer each time a timer underflows, and a timer interrupt request occurs. [Use ] * Generation of cyclic interrupts * Clock function (measurement of one second) Application example 1 * Control of a main routine cycle
[Function 3 ] Output of Rectangular waveform (Timers 1 and 3) The output level of the TOUT pin is inverted every time a timer underflows. To output long-interval rectangular waveforms (when division of 8 bits or more is necessary), the Timers 2 and 3 are connected . [Use ] * A piezoelectric buzzer output Application example 2 * Generation of the remote-control carrier waveforms
[Function 4] Count of External pulse (Timers 2 and 4) External pulses input to the CNTR pin are selected as a timer count source. [Use ] * Measurement of frequency (judging if the Video synchronization signal exits) Application example 3 * Division of external pulses and generation of interrupts in a cycle based on an external pulse. (count of a reel pulse)
[Function 5 ] Output of PWM signal (Timer 6) The pulses with each specified intervals of "H" and "L" are output. [Use ] * Control of an electronic volume (connected with VCA)
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(2) Timer application example 1: Clock function (measurement of one second)
3819 Group 2.2 Timer
Outline : The input clock is divided by a timer so that the clock counts up every second. Specifications : * The clock f(XIN) = 4.19 MHz (2
22
) is divided by a timer.
* The Timer 3 interrupt request bit is checked in the main routine, and the clock is counted up when an interrupt request occurs. * Another interrupt processing is executed in a parallel, so a timer interrupt occurs every 244 s. Figure 2.2.11 shows a connection of timers and a setting of division ratios, Figures 2.2.12 and 2.2.13 show a setting of related registers, and Figure 2.2.14 shows a control procedure.
Fixed f(XIN) = 4.19 MHz Timer 1 Timer 2 Timer 3 Timer 3 interrupt request bit
1/16
1/64
1/256
1/16
0 or 1
1 second
0 or 1
244 s 0 : No interrupt request 1 : Interrupt request
Timer 1 interrupt request bit
Fig. 2.2.11 Connection of timers and setting of division ratios [Clock function]
Timer 12 mode register (Address:28 16) T12M 000 001
Timer 1 count : Stopped Set to "0" at starting to count Timer 2 count : Operating Timer 1 count source : f(X IN)/16 Timer 2 count source : Timer 1 underflow Timer 1 output selection : I/O port
Timer 34 mode register (Address:29 16) T34M 0 1 0
Timer 3 count : Operating Timer 3 count source : Timer 2 underflow Timer 3 output selection : I/O port
Fig. 2.2.12 Setting of related registers (1) [Clock function]
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3819 Group 2.2 Timer
Timer 1 (Address:2016) T1 63 Timer 2 (Address:2116) T2 255 Timer 3 (Address:2216) T3 15 Interrupt control register 1 (Address:3E16) ICON1 01
Set "division ratio - 1"
Timer 1 interrupt : Enabled Timer 2 interrupt : Disabled
Interrupt control register 2 (Address:3F16) ICON2 0 0
Timer 3 interrupt : Disabled
Interrupt request register 1 (Address:3C16) IREQ1
Timer 1 interrupt request Timer 2 interrupt request
Interrupt request register 2 (Address:3D16) IREQ2
Timer 3 interrupt request (becomes "1" every second)
Fig. 2.2.13 Setting of related registers (2) [Clock function]
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Control procedure : Figure 2.2.14 shows a control procedure.
3819 Group 2.2 Timer
RESET
Initialization SEI T12M T34M ICON1 ICON2 T1 T2 T3 .... .... (Address:2816) 000000012 (Address:2916) 000001002 (Address:3E16), bit6 1 (Address:3F16), bit0 0 (Address:2016) (Address:2116) (Address:2216) 64 - 1 256 - 1 16 - 1 0
q
All interrupts : Disabled Connect the Timers 1 to 3. Timer 1 interrupt : Enabled Set "division ratio - 1" to each timer.
q
q
q
T12M (Address:2816), bit0 CLI ....
....
q
Start the timer counting. Interrupts : Enabled
q
Clock stop? N IREQ2 (Address:3D 16), bit0? 1
Y
q
Check if the clock has already been set.
0
q
Check a lapse of 1 second.
q
IREQ2 (Address:3D 16), bit0 i Count up clock Second-Year
0
Set the Timer 3 interrupt request bit to "0". (When an interrupt is not used, set to "0" by software.)
q
Count up the clock.
Main processing
[Processing for completion of setting clock] ( Note)
q
Specify so that all processing within the loop marked i is repeated in a cycle of 1 second or less in the main processing. When restarting the clock from zero second after completing to set the clock, reset timers. Reset the Timers 2 and 3 in this order. However, the Timer 1 should not be reset since it is used to generate an interrupt every 244 s.
(Address:2116) T2 (Address:2216) T3 IREQ2 (Address:3D16), bit0
Note : This processing is performed only at completing to set the clock.
Fig. 2.2.14 Control procedure [Clock function]
....
256 - 1 16 - 1 0
q
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(3) Timer application example 2: Piezoelectric buzzer output
3819 Group 2.2 Timer
Outline : The rectangular waveform output function of a timer is applied for a piezoelectric buzzer output. Specifications : * The rectangular waveform, 2 kHz (2048 Hz) which is divided clock f(XIN) = 4.19 MHz is output from the T3OUT pin. * The level of the T3OUT pin fixes to "H" while a piezoelectric buzzer output is stopped. Figure 2.2.15 shows an example of a peripheral circuit, and Figure 2.2.16 shows a connection of the timer and setting of the division ratio.
The "H" level is output while a piezoelectric buzzer output is stopped.
3819 group
T3OUT
PiPiPi....
244 s
244 s Set a division ratio so that the underflow output cycle of the Timer 3 becomes this value.
Fig. 2.2.15 Example of a peripheral circuit
Fixed f(XIN) = 4.19 MHz
Timer 3
Fixed
1/16
1/64
1/2
T3OUT
Fig. 2.2.16 Connection of the timer and setting of the division ratio [Piezoelectric buzzer output]
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3819 Group 2.2 Timer
Timer 34 mode register (Address:2916) T34M 1 0 0
Timer 3 count : Operating Timer 3 count source : f(X IN)/16 Timer 3 output selection : Set to "1" during outputting a piezoelectric buzzer. Set to "0" during stopping outputting of a piezoelectric buzzer.
Timer 3 (Address:22 16) T3 63
Set "division ratio - 1"
Fig. 2.2.17 Setting of related registers [Piezoelectric buzzer output] Control procedure : Figure 2.2.18 shows a control procedure.
RESET Initialization P4 P4D .... .... (Address:0816), bit7 (Address:0916), bit7 1 1
q
Set the port condition during stopping outputting a piezoelectric buzzer ( "H" level output ). Timer 3 interrupts : Disabled The T3OUT output is stopped at this point (stop outputting a piezoelectric buzzer ).
ICON2 (Address:3F16), bit7, bit0 0 T34M (Address:2916) 010000002 (Address:2216) T3 64 - 1 ....
q
q
Main processing
The piezoelectric buzzer request occured in the main processing is processed in the output unit.
Output unit A piezoelectric buzzer is requested? N T34M (Address:29 16), bit6 0
Y
T34M (Address:2916), bit6
1
During stopping outputting a piezoelectric buzzer (P4
7)
During outputting a piezoelectric buzzer (T3 OUT)
Fig. 2.2.18 Control procedure [Piezoelectric buzzer output]
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(4) Timer application example 3 : Measurement of frequency (judging if Video synchronization signal exists)
3819 Group 2.2 Timer
Outline : The pulses input to the External count input pin (CNTR) are counted by a timer to judge if the frequency is within a certain range. Specifications : * The Video synchronization signal is input to the CNTR1 pin and counted by the Timer 4. * A count value is read out at the interval of about 2 ms (Timer 1 interrupt interval : 244 s ! 8). When the count value is 28 to 40, it is regarded as the existence of the Video synchronization signal. * * Because the timer is a down-counter, the count value is compared with 227 to 215. * 227 to 215 = 255 (initialized value of counter) - 28 to 40 (the number of valid value). Figure 2.2.19 shows a method for judging if Video synchronization signal exists, and Figure 2.2.20 shows a setting of related registers.
Video synchronization signal 63.5 s (15.7 kHz)
244 s ! 8 63.5 s
= 31 counts
Fig 2.2.19 A method for judging if Video synchronization signal exists
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3819 Group 2.2 Timer
Timer 12 mode register (Address:2816) T12M 0 0 1
Timer 1 count : Stopped Set to "0" at starting to count. Timer 1 count source : f(XIN)/16 Timer 1 output selection : I/O port (Not to be used timer 1 output)
Timer 34 mode register (Address:2916) T34M 10 0
Timer 4 count : Operating Timer 4 count source : External count input from CNTR1 pin.
Timer 1 (Address:2016) T1 63 Timer 4 (Address:2316) T4 255
Set "255" to this register immediately before count- ing pulse. (After a certain time, this value is decreased by the number of input pulses) Set "division ratio - 1"
Interrupt control register 1 (Address:3E16) ICON1 1
Timer 1 interrupt : Enabled
Interrupt control register 2 (Address:3F16) ICON2 0 0
Timer 4 interrupt : Disabled
Interrupt request register 2 (Address:3D16) IREQ2 0
Judgment of Timer 4 interrupt request bit (When this bit is set to "1" at reading out the count value of the timer 4 (address:2316), 256 pulses or more are input (at setting 255 to the Timer 4).)
Fig. 2.2.20 Setting of related registers [Measurement of frequency]
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Control procedure : Figure 2.2.21 shows a control procedure.
3819 Group 2.2 Timer
RESET
Initialization SEI T12M T34M ICON1 ICON2 T1 .... .... .... (Address:2816) 000000012 (Address:2916) 001000002 (Address:3E16), bit6 1 (Address:3F16), bit7 0 (Address:2016) 64 - 1 0
q
All interrupts : Disabled Select the input pulse from the CNTR 1 pin as the Timer 4 count source. Timer 1 interrupt : Enabled Set the division ratio so that the Timer 1 interrupt occurs every 244 s. Start a timer counting. Interrupts : Enabled
q
q
T12M (Address:2816), bit0 CLI ....
q
q
~ ~
Timer 1 interrupt processing routine 1/8
q
Set so that the processing Synchronizing signal judgment is performed every time eight Timer 1 interrupts occur. When the count value is 256 or more, the processing is performed as out of range. Read the count value. Store the count value in the accumulator (A).
1
q
IREQ2 (Address:3D 16), bit1? 0
q
(A)
T4 (Address:23 16)
q
214 < (A) < 228? Out of range FSync 0
In range
q
q
Compare the count value read with the reference value. Store the comparison result in flag FSync. 1
FSync
(Address:2316) T4 IREQ2 (Address:3D16), bit1
256 - 1 0
q q
Initialize the count value. Set the Timer 4 interrupt request bit to "0".
Processing for a result of judgment
RTI
Fig. 2.2.21 Control procedure [Measurement of frequency]
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2.3 Serial I/O
2.3.1 Related registers
3819 Group 2.3 Serial I/O
Serial I/O automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O automatic transfer data pointer (SIODP) [Address:1816]
B
Function
At reset
RW
0 Indicate an address of Serial I/O automatic transfer RAM. 1 2 3 4 5 Nothing is allocated for these bits. These are write disabled bits. 6 When these bits are read out, the values are "0." 7
? ? ? ? ? 0 0 0
! ! !
Fig. 2.3.1 Structure of Serial I/O automatic transfer data pointer
Serial I/O 1 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O 1 control register (SIO1CON) [Address:1916]
B
Name
b2 b1b0
Function
000 : f(XIN)/8 or f(XCIN)/8 001 : f(XIN)/16 or f(XCIN)/16 010 : f(XIN)/32 or f(XCIN)/32 011 : f(XIN)/64 or f(XCIN)/64 110 : f(XIN)/128 or f(XCIN)/128 111 : f(XIN)/256 or f(XCIN)/256 0 : I/O port T 1 : SOUT1, SCLK11, SCLK12 signal pins 0 : I/O port T ( Note) 1 : SRDY1/CS signal pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
At reset
RW
0 Internal synchronous clock
selection bits
0 0 0 0 0 0 0 0
1 2 3 Serial I/O 1 port selection bit 4 5 6 7
(P65,P66,P67T ) SRDY1 output selection bit (P67) Transfer direction selection bit Synchronous clock selection bit P65/SOUT1 P-channel output disable bit
T
Valid only in the Serial I/O automatic transfer mode
Note : When an external clock is selected in the serial I/O 1 automatic transfer mode, the SRDY1 signal pin is used as the CS signal input pin.
Fig. 2.3.2 Structure of Serial I/O 1 control register
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3819 Group 2.3 Serial I/O
Serial I/O automatic transfer control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O automatic transfer control register (SIOAC) [Address:1A16]
B
Name
Function
0 : Serial I/O ordinary mode (serial I/O 1 interrupt) 1 : Automatic transfer mode (serial I/O automatic transfer interrupt) 0 : Transfer completion 1 : Transferring (starts by writing "1") 0 : Fullduplex (transmit / receive) mode 1 : Transmit-only mode
At reset
RW
0 Automatic transfer control bit
0
1 Automatic transfer start bit
0 0
2 Transfer mode switch bit
3 Synchronous clock output
0 : SCLK11 pin selection bit 1 : SCLK12 4 Nothing is allocated for these bits. These are write disabled bits. 5 When these bits are read out, the values are "0."
0 0 0 0 0
! ! ! !
6 7
Fig. 2.3.3 Structure of Serial I/O automatic transfer control register
Serial I/O 1 register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O 1 register (SIO1) [Address:1B16]
B
q
Function
At transmitting : Set a transmission data. At receiving : Store a reception data.
At reset
RW
0 A shift register for serial transmission and reception. 1 2 3 4 5 6 7
q
? ? ? ? ? ? ? ?
Fig. 2.3.4 Structure of Serial I/O 1 register
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3819 Group 2.3 Serial I/O
Serial I/O automatic transfer interval register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O automatic transfer interval register (SIOAI) [Address:1C16]
B 0 Ti = (n + 2) ! Tc 1 2 3 4
Function
Ti = a length of transfer interval n = a setting value Tc = a length of a bit of transfer clock
At reset
RW
0 0 0 0 0 0 0 0
! ! !
5 Nothing is allocated for these bits. These are write disabled bits. 6 When these bits are read out, the values are "0." 7
Fig. 2.3.5 Structure of Serial I/O automatic transfer interval register
Serial I/O 2 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O 2 control register (SIO2CON) [Address:1D 16]
B
Name
b2 b1b0
Function
000 : f(XIN)/8 or f(XCIN)/8 001 : f(XIN)/16 or f(XCIN)/16 010 : f(XIN)/32 or f(XCIN)/32 011 : f(XIN)/64 or f(XCIN)/64 110 : f(XIN)/128 or f(XCIN)/128 111 : f(XIN)/256 or f(XCIN)/256 0 : I/O port 1 : SOUT2, SCLK2 signal pins 0 : I/O port 1 : SRDY2 signal pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
At reset
RW
0 Internal synchronous clock
selection bits
0 0 0 0 0 0 0 0
1 2 3 Serial I/O 2 port selection bit
(P51,P52 ) 4 SRDY2 output selection bit (P53) Transfer direction selection bit 5
6 Synchronous clock selection
bit
7 P51/SOUT2 P-channel output
disable bit
Fig. 2.3.6 Structure of Serial I/O 2 control register
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3819 Group 2.3 Serial I/O
Serial I/O 3 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O 3 control register (SIO3CON) [Address:1E16]
B
Name
b2 b1b0
Function
000 : f(XIN)/8 or f(XCIN)/8 001 : f(XIN)/16 or f(XCIN)/16 010 : f(XIN)/32 or f(XCIN)/32 011 : f(XIN)/64 or f(XCIN)/64 110 : f(XIN)/128 or f(XCIN)/128 111 : f(XIN)/256 or f(XCIN)/256 0 : I/O port 1 : SOUT3, SCLK3 signal pins 0 : I/O port 1 : SRDY3 signal pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
At reset
RW
0 Internal synchronous clock selection bits 1 2 3 Serial I/O 3 port selection bit 4 5 6 7
(P55,P56 ) SRDY3 output selection bit (P57) Transfer direction selection bit Synchronous clock selection bit P55/SOUT3 P-channel output disable bit
0 0 0 0 0 0 0 0
Fig. 2.3.7 Structure of Serial I/O 3 control register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address:3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T
0 INT0 interrupt request bit 1 INT1/ZCR interrupt request bit 2
q q
0 0 0
INT2 interrupt request bit Remote control/counter overflow interrupt request bit
3
Serial I/O 1 interrupt request bit q Serial I/O automatic transfer interrupt request bit
q
0
T
4 Serial I/O 2 interrupt request
bit Serial I/O 3 interrupt request 5 bit 6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
0 0 0 0
T T T T
T "0" is set by software, but not "1."
Fig. 2.3.8 Structure of Interrupt request register 1
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3819 Group 2.3 Serial I/O
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address:3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1/ZCR interrupt enable bit 2
q q
0 0 0
INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit Serial I/O1 interrupt enable bit Serial I/O automatic transfer interrupt enable bit
3
q
0
q
4 Serial I/O 2 interrupt enable
bit 5 Serial I/O 3 interrupt enable bit 6 Timer 1 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
7 Timer 2 interrupt enable bit
Fig. 2.3.9 Structure of Interrupt control register 1
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2.3.2 Serial I/O connection examples (1) Control of peripheral IC equipped with CS pin In any application, the automatic transfer function is available.
3819 Group 2.3 Serial I/O
Figure 2.3.10 shows connection examples of a peripheral IC equipped with the CS pin.
(1) Only transmission (using the S IN pin as an I/O port) Port SCLK SOUT 3819 group CS CLK DATA Peripheral IC (OSD controller etc.)
(2) Transmission and reception
Port SCLK SOUT SIN 3819 group
CS CLK IN OUT Peripheral IC (E 2 PROM etc.)
(3) Transmission and reception (Pins SIN and SOUT are connected) (Pins IN and OUT in peripheral IC are connected) Port SCLK SOUT SIN 3819 group CS CLK IN OUT Peripheral IC T (E 2 PROM etc.)
(4) Connecting ICs
Port SCLK SOUT SIN Port 3819 group
CS CLK IN OUT Peripheral IC 1
T The OUT pin of the peripheral IC is an N-channel open-drain output. It is in high impedance during receiving data. Note : "Port" is an output port controlled by software.
CS CLK IN OUT Peripheral IC 2
Fig. 2.3.10 Serial I/O connection examples (1)
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(2) Connection with microcomputer Figure 2.3.11 shows connection examples of the other microcomputers.
3819 Group 2.3 Serial I/O
(1) Selecting an internal clock (Possible of using an automatic transfer function) SCLK SOUT SIN 3819 group CLK IN OUT Microcomputer
(2) Selecting an external clock (Possible of using an automatic transfer function) SCLK SOUT SIN 3819 group CLK IN OUT Microcomputer
(3) Using the SRDY signal output function (Selecting an external clock, and not using an automatic transfer function)
(4) Using the CS signal reception function (Selecting an external clock, and using an automatic transfer function)
SRDY SCLK SOUT SIN 3819 group
RDY CLK IN OUT Microcomputer
CS SCLK SOUT SIN 3819 group
CS CLK IN OUT Microcomputer
(5) Using the CLK signal output pin switch (SCLK12) function (Selecting an internal clock, and using an automatic transfer function)
SCLK11 SOUT SIN SCLK12 Port 3819 group
CLK IN OUT
Microcomputer
CLK IN OUT CS Peripheral IC
Fig. 2.3.11 Serial I/O connection examples (2)
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2.3.3 Setting of serial I/O mode
3819 Group 2.3 Serial I/O
Whether SRDY signal output, CS signal receive and CLK signal output pin switch (SCLK12) functions can be selected to use or not by the following conditions: * Serial I/O circuits ( serial I/O 1 or serial I/O 2 ) * The automatic transfer function is ON or OFF ( at the serial I/O 1 only) * Transfer clock ( internal clock or external clock) Figure 2.3.12 shows a setting of serial I/O mode.
Internal clock Automatic transfer function OFF External clock not output SRDY signal Serial I/O 1 use SCLK12 pin Internal clock not use SCLK12 pin Automatic transfer function ON External clock not use CS function use CS function
output SRDY signal
Internal clock Serial I/O 2 Serial I/O 3 output SRDY signal External clock not output SRDY signal
Fig. 2.3.12 Setting of Serial I/O mode
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2.3.4 Serial I/O application examples (1) Output of serial data (control of a peripheral IC)
3819 Group 2.3 Serial I/O
Outline : The port is connected to the CS pin of a peripheral IC and the serial transmission is controlled.
P67 P66/SCLK11 P65/SOUT1 3819 group
CS CLK DATA
CS CLK DATA Peripheral IC
Fig. 2.3.13 Connection diagram [Output of serial data] Specifications : * The Serial I/O 1 is used (the automatic transfer function is not used) * Synchronous clock frequency: 131 kHz ( f(XIN) = 4.19 MHz is divided by 32) * Transmission direction: LSB first * The Serial I/O 1 interrupt is not used. * The Port P67 is connected to the CS pin ("L" active) of the peripheral IC for a transmission control (the output level of the port P67 is controlled by software). Figre 2.3.14 shows an output timing chart of serial data.
CS
CLK
DATA
DO0
DO1
DO2
DO3
Fig. 2.3.14 Timing chart [Output of serial data]
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3819 Group 2.3 Serial I/O
Serial I/O 1 control register (Address:1916) SIO1CON 01001010
Internal synchronous clock : f(X IN)/32 Use the Serial I/O 1 Not use the SRDY1 signal output function LSB first Internal clock CMOS output
Serial I/O automatic transfer control register (Address:1A 16) SIOAC 0
Serial I/O ordinary mode
Port P6 register (Address:0C16) P6 1
Set P67 output level to "H"
Port P6 direction register (Address:0D16) P6D 1
Set P67 to output mode
Interrupt control register 1 (Address:3E16) ICON1 0
Serial I/O 1 interrupt : Disabled
Interrupt request register 1 (Address:3C16) IREQ1
Serial I/O 1 interrupt request (Using this bit, check the completion of transmitting 1-byte base data (becomes "1" when the data transmission is completed).)
Fig. 2.3.15 Setting of related registers [Output of serial data]
Serial I/O 1 register (Address:1B16) SIO1
Set a transmission data. Check that transmission of the previous data is completed before writing data (bit 3 of the Interrupt request register 1 is set to "1").
Fig. 2.3.16 Setting of transmission data [Output of serial data]
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3819 Group 2.3 Serial I/O
Control procedure :When the registers are set as shown in Fig. 2.3.15, the Serial I/O 1 can transmit one-byte data simply by writing data to the Serial I/O 1 register. Thus, after setting the CS signal to "L", write the transmission data to the Serial I/O 1 register on a one-byte base, and return the CS signal to "H" when the desired number of bytes have been transmitted.
RESET
Initialization SIO1CON (Address:1916) 010010102 (Address:1A16) SIOAC 000000002 (Address:0C16), bit7 P6 1 (Address:0D16), bit7 P6D 1
.... ....
q
Set the Serial I/O 1. Set the CS signal output level to "H." Set the CS signal output port.
q q
P6 (Address:0C 16), bit7
0
q
Set the CS signal output level to "L."
q
IREQ1 (Address:3C 16), bit3
0
Set the Serial I/O 1 interrupt request bit to "0".
SIO1 (Address:1B 16)
a transmission data
q
Write a transmission data. (start to transmit 1-byte data)
IREQ1 (Address:3C 16), bit3? 1
0
q
Check the completion of transmitting 1-byte data.
N
q
Complete to transmit data?
q
Y
q
Use any of RAM area as a counter for counting the number of transmitted bytes. Check that transmission of the target number of bytes has been completed. Return the CS signal output level to "H" when transmission of the target number of bytes is completed.
P6 (Address:0C16), bit7
1
Fig. 2.3.17 Control procedure [Output of serial data]
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(2) Data transmission or reception using automatic transfer
3819 Group 2.3 Serial I/O
Outline : Serial transmission or reception is controlled by using a serial automatic transfer function.
P66/SCLK11 P65/SOUT1 P64/SIN1 3819 group
CLK OUT IN
CLK IN OUT Sub-microcomputer
Fig. 2.3.18 Connection diagram [Data transmission or reception using automatic transfer] Specifications : * The Serial I/O 1 is used (the automatic transfer function is used). * Transmission clock frequency: 131 kHz (f(XIN) = 4.19 MHz is divided by 32) * Transmission direction : LSB first * Number of bytes for transmission or reception : each 8 bytes/block * Transmission interval: 244 s (corresponding to a transmission clock of 32 bits) * The Serial I/O automatic transfer interrupt is not used. Figure 2.3.19 shows a transmission or reception timing chart using an automatic transfer.
1 block CLK
OUT
DO0
DO1
DO2
DO7
DO0
DO1
IN
DI0
DI1
DI2
DI7
DI0
DI1
A cycle of blocks is controlled by software. (synchronize with a main routine.)
Fig. 2.3.19 Timing chart [Data transmission or reception using automatic transfer]
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3819 Group 2.3 Serial I/O
Serial I/O1 control register (Address:1916) SIO1CON 01001010
Internal synchronous clock : f(X IN)/32 Use Serial I/O 1 Not use SRDY1 signal output function LSB first Internal clock CMOS output
Serial I/O automatic transfer control register (Address:1A 16) SIOAC 0001
Automatic transfer mode Set to a transfer completion state (stop transferring) in initialization. (After setting a transmission data, set to "1" at starting automatic transfer.) Fullduplex (transmit/receive) mode Synchronous clock output pin : S CLK11
Serial I/O automatic transfer interval register (Address:1C16) SIOAI 11110
Set an interval of transfer clock,32 bits. (set so that "setting value + 2 = 32.")
Serial I/O automatic transfer data pointer (Address:1816) SIODP 00111
Set "the number of transfer bytes - 1" (in this example, (8 bytes - 1) = 7 is set after completing to transfer 1-byte data, and before starting to transfer the next data.)
Interrupt control register 1 (Address:3E16) ICON1 0
Serial I/O automatic transfer interrupt : Disabled
Fig. 2.3.20 Setting of related registers [Data transmission or reception using automatic transfer]
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3819 Group 2.3 Serial I/O
Serial I/O1 register (Address:1B16) SIO1
This register is not used at using automatic transfer.
Serial I/O automatic transfer RAM (Address:0F0016 to 0F1F16)
SIORAM 0F0016 0F0116 DO7 DO6 Execution of automatic transfer 0F0016 0F0116 DI7 DI6
0F0616 0F0716
Fig. 2.3.21 Setting of transmission data [Data transmission or reception using automatic transfer]
.....
DO1 DO0
In this example, address "0F0816 to 0F1F16 " which are not used for an automatic transfer can be used as ordinary RAM.
.....
0F0616 0F0716
3819 Group USER'S MANUAL
.....
DI1 DI0
.....
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3819 Group 2.3 Serial I/O
Control procedure : In this example, a serial communication is performed at the beginning of the main routine which loops in a certain cycle.
RESET Initialization
q q
010010102 SIO1CON (Address:1916) (Address:1A16) 000000012 SIOAC (Address:1C16) 30 SIOAI (Address:1816) SIODP 8-1 (Address:3E16), bit3 0 ICON1 ...
Serial I/O automatic transfer RAM (Address:0F0016 to 0F0716)
RAM for processing of a reception data
Fig. 2.3.22 Control procedure [Data transmission or reception using automatic transfer]
...
Initialize the serial I/O 1 Set the related functions for using automatic transfer.
Has the time specified for the cycle control of a main routine elapsed?
N
q
q
Y
a transmission data
q
Generate the timing of a certain cycle by using the timer or other functions. Control so that the main routine is executed in a certain cycle. Set one block (8 byte) of transmission data in the RAM.
SIODP (Address:18 16)
7
q
Set the data pointer (set "8 byte - 1").
SIOAC (Address:1A 16), bit 1
1
q
Start the automatic transfer. It is possible to execute the other processing during an automatic transfer. (a part of the main processing is executed.) Check the completion of an automatic transfer. Transfer a data stored to the Serial I/O automatic transfer RAM to RAM for processing of reception data. Perform the following processing in the main processing. 1. The processing of the data transferred into the RAM for processing of reception data. 2. The preparation of the next transmission data.
q
SIOAC (Address:1A 16), bit1? 0
Serial I/O automatic transfer RAM (Address:0F0016 to 0F0716)
1
q
q
Main processing
q
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3819 Group 2.3 Serial I/O
(3) Cyclic transmission or reception of block data (data of a specified number of bytes) between microcomputers [without using an automatic transfer] Outline : When a clock synchronous serial I/O is used for communication, synchronization of the clock and the data between the transmitter and receiver sides may be lost because of noise included in the synchronizing clock. Thus, it is necessary to be corrected constantly. This "heading adjustment" is carried out by using the interval between blocks in this example.
SCLK SIN SOUT Master unit
SCLK SIN SOUT Slave unit
Fig. 2.3.23 Connection diagram [Cyclic transmission or reception of block data between microcomputers] Specifications : * Synchronous clock frequency : 131 kHz (f(XIN) = 4.19 MHz is divided by 32) * Byte cycle : 488 s * Number of bytes for transmission or reception : each 8 byte/block * Block transmission cycle : 16 ms * Block transmission period : 3.5 ms * Interval between blocks : 12.5 ms * Heading adjustive time : 8 ms * Transmission direction : LSB first Limitations of the specifications 1. Reading of the reception data and setting of the next transmission data must be completed within the time obtained from "byte cycle - time for transmitting 1-byte data" (in this example, the time taken from generating of the Serial I/O 1 interrupt request to generating of the next synchronizing clock is 431 s). 2. "Heading adjustive time < interval between blocks" must be satisfied. 3. Although the transmission direction can be switched for the Serial I/O of 3819 group, it cannot be switched for some serial I/Os of 740 family including 38000 series (only LSB first). Be sure to check when deciding specifications.
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3819 Group 2.3 Serial I/O
The communication is performed according to the timing shown below. In the slave unit, when a synchronizing clock is not input within a certain time (heading adjustive time), the next clock input is processed as the beginning (heading) of a block. When a clock is input again after one block (8 byte) is received, the clock is ignored. Figure 2.3.25 shows a setting of related registers.
D0
D1
D2
D7
D0
Byte cycle Block transmission period Block transmission cycle Heading adjustive time Processing for heading adjustment Interval between blocks
Fig. 2.3.24 Timing chart [Cyclic transmission or reception of block data between microcomputers]
Master unit
Serial I/O 1 control register (Address:1916) SIO1CON 0 1 0 0 1 0 1 0
Slave unit
Serial I/O 1 control register (Address:1916) SIO1CON 0 0 0 0 1
Internal synchronous clock : f(XIN)/32 Use the Serial I/O 1 Not use the SRDY1 signal output function LSB first Internal clock CMOS output
Not be effected by external clock Use the Serial I/O 1 Not use the SRDY1 signal output function LSB first External clock CMOS output
[When using the Serial I/O 1]
Serial I/O automatic transfer control register (Address:1A16) SIOAC
0
Note : When an automatic transfer function is not used, the S CLK11 is used as an I/O pin for a synchronizing clock (the SCLK12 is not selected).
Serial I/O ordinary mode
Fig. 2.3.25 Setting of related registers [Cyclic transmission or reception of block data between microcomputers]
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Control procedure :
3819 Group 2.3 Serial I/O
(1) Control in the master unit After a setting of the related registers is completed as shown in Figure 2.3.25, in the master unit transmission or reception of one-byte data is started simply by writing transmission data to the Serial I/O 1 register. To perform the communication in the timing shown in the specifications, therefore, take the timing into account and write transmission data. Read out the reception data when the Serial I/O 1 interrupt request bit is set to "1", or before the next transmission data is written to the Serial I/O 1 register. A processing example in the master unit using timer interrupts is shown below.
Interrupt processing routine executed every 488 s
Within a block transfer period? Y Read a reception data
N
q
Generate a certain block interval by using a timer or other functions.
Count a block interval counter
q
Check the block interval counter and determine to start of a block transfer. N
Complete to transmit a block? N Write a transmission data
Y
Start a block transfer? Y Write the first transmission data (first byte) in a block
RTI
Fig. 2.3.26 Control in the master unit
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3819 Group 2.3 Serial I/O
(2) Control in the slave unit After a setting of the related registers is completed as shown in Figure 2.3.25, the slave unit becomes the state which is received a synchronizing clock at all times, and the Serial I/O 1 interrupt request bit is set to "1" every time an 8-bit synchronous clock is received. For transmitting or receiving data according to the synchronizing clock input in the timing shown in the specifications, read out the reception data and write the next transmission data to the Serial I/O 1 register in the following conditions. * When the Serial I/O 1 interrupt occurs. * When the Serial I/O 1 interrupt request bit is set to "1" as the result of checking. When the Serial I/O 1 interrupt request bit is not set to "1" within a certain time (heading adjustive time), the first byte of the transmission data in a block is written to the Serial I/O 1 register, then the next reception data is processed as the first byte of the reception data in a block. A processing example in the slave unit using serial I/O interrupts and timer interrupts (for a heading adjustment) is shown below.
Serial I/O 1 interrupt processing routine
q
Timer interrupt processing routine Check the received byte counter to judge if a block has been transfered.
Within a block transfer period? Y Read a reception data
N
Heading adjustive counter - 1
Heading adjustive counter = 0? Y
N
A received byte counter +1
Write the first transmission data (first byte) in a block
A received byte counter A received byte counter 8? N Write a transmission data Write any data (FF16) Y
0
RTI
Heading adjustive counter
Initialized value (Note)
RTI
Note : In this example, set the value which is equal to the heading adjustive time divided by the timer interrupt cycle as the initialized value of the heading adjustive counter. For example : When the heading adjustive time is 8ms and the timer interrupt cycle is 1ms, set 8 as the initialized value.
Fig. 2.3.27 Control in the slave unit
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2.4 A-D conversion
2.4.1 Related registers
3819 Group 2.4 A-D conversion
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0 AD/DA control register (ADCON) [Address:2C16]
B
Name
b3 b2 b1 b0
Function
0 0 0 0 : P70/AN0 0 0 0 1 : P71/AN1 0 0 1 0 : P72/AN2 0 0 1 1 : P73/AN3 0 1 0 0 : P74/AN4 0 1 0 1 : P75/AN5 0 1 1 0 : P76/AN6 0 1 1 1 : P77/AN7 1 0 0 0 : P50/SIN2/AN8 1 0 0 1 : P51/SOUT2/AN9 1 0 1 0 : P52/SCLK2/AN10 1 0 1 1 : P53/SRDY2/AN11 1 1 0 0 : P54/SIN3/AN12 1 1 0 1 : P55/SOUT3/AN13 1 1 1 0 : P56/SCLK3/AN14 1 1 1 1 : P57/SRDY3/AN15 1 : Conversion completed
At reset
RW
0 Analog input pin selection bits
0
1
0
2
0
3
0
4 A-D conversion completion bit 0 : Conversion in progress 5 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0." 0 : Disable 6 D-A output enable bit 1 : Enable Nothing is allocated for this bit. This is a write disabled bit. 7 When this bit is read out, the value is "0."
1 0 0 0
! !
Fig. 2.4.1 Structure of AD/DA control register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address:2D16]
B Function 0 The read-only register which A-D conversion results are stored. 1 2 3 4 5 6 7
At reset
RW
! ! ! ! ! ! ! !
? ? ? ? ? ? ? ?
Fig. 2.4.2 Structure of A-D conversion register
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3819 Group 2.4 A-D conversion
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address:3D16]
b
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T
0 Timer 3 interrupt request bit 1 Timer 4 interrupt request bit 2 Timer 5 interrupt request bit 3 Timer 6 interrupt request bit 4 INT3 interrupt request bit 5
q q
0 0 0 0 0 0
INT4 interrupt request bit A-D conversion interrupt request bit
6
q
q
FLD blanking interrupt 0 : No interrupt request request bit 1 : Interrupt request FLD digit interrupt request bit
0
T
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0." T "0" is set by software, but not "1."
0
T
Fig. 2.4.3 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address:3F16]
b
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 Timer 3 interrupt enable bit 1 Timer 4 interrupt enable bit 2 Timer 5 interrupt enable bit 3 Timer 6 interrupt enable bit 4 INT3 interrupt enable bit 5
q q
0 0 0 0 0 0
INT4 interrupt enable bit A-D conversion interrupt enable bit FLD blanking interrupt enable bit FLD digit interrupt enable bit
6
q
0 0
q
7 Fix this bit to "0."
Fig. 2.4.4 Structure of Interrupt control register 2
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2.4.2 A-D conversion application example Conversion of Analog input voltage
3819 Group 2.4 A-D conversion
Outline : The analog input voltage input from the sensor is converted into digital values. Figure 2.4.5 shows a connection diagram, and Figure 2.4.6 shows a setting of related registers.
VCC VREF P70/AN0
Sensor
VSS
AVSS
3819 group
Fig. 2.4.5 Connection diagram [Conversion of Analog input voltage] Specifications : * The AN0 pin is used as an analog input pin. * The analog input voltage input from the sensor is converted into digital values.
AD/DA control register (Address:2C16) ADCON 0000
Analog input pin selection : P70/AN0 Start A-D conversion
A-D conversion register (Address:2D16) AD
(read-only)
Store a result of A-D conversion
Note : Read out a result of A-D conversion after bit 4 of the AD/DA control register (ADCON) is set to "1".
Fig. 2.4.6 Setting of related registers [Conversion of Analog input voltage]
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3819 Group 2.4 A-D conversion
Control procedure : By setting the related registers as shown in Figure 2.4.6, the analog input voltage input from the sensor are converted into digital values.
~ ~
ADCON (Address:2C16), bit0 - bit3 ADCON (Address:2C16), bit4 0000 2 0
q q
Select the AN0 pin as an analog input pin. Start A-D conversion.
ADCON (Address:2C 16), bit4? 1 Read out AD (Address:2D 16)
0
q
Check the completion of A-D conversion.
q
Read out the conversion result.
~ ~
Fig. 2.4.7 Control procedure [Conversion of Analog input voltage]
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2.5 FLD controller
2.5.1 Related registers
Port P0 segment/digit switch register
b7 b6 b5 b4 b3 b2 b1 b0
3819 Group 2.5 FLD controller
Port P0 segment/digit switch register (P0SDR) [Address:3216]
Name B 0 Port P0 segment/digit
switch register
Function
0 : DIG0 1 : SEG32 0 : DIG1 1 : SEG33 0 : DIG2 1 : SEG34 0 : DIG3 1 : SEG35 0 : DIG4 1 : SEG36 0 : DIG5 1 : SEG37 0 : DIG6 1 : SEG38 0 : DIG7 1 : SEG39
At reset
RW
0 0 0 0 0 0 0 0
1 2 3 4 5 6 7
Fig. 2.5.1 Structure of Port P0 segment/digit switch register
Port P2 digit/port switch register
b7 b6 b5 b4 b3 b2 b1 b0 Port P2 digit/port switch register (P2DPR) [Address:3316]
B
register
Name
0 : Port P20 1 : DIG16 0 : Port P21 1 : DIG17 0 : Port P22 1 : DIG18 0 : Port P23 1 : DIG19
Function
output-only output-only output-only output-only
At reset
RW
0 Port P2 digit/port switch 1 2 3
0 0 0 0 0 0 0 0
! ! ! !
4 Nothing is allocated for these bits. These are write disabled bits. 5 When these bits are read out, the values are "0." 6 7
Fig. 2.5.2 Structure of Port P2 digit/port switch register
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3819 Group 2.5 FLD controller
Port P8 segment/port switch register
b7 b6 b5 b4 b3 b2 b1 b0 Port P8 segment/port switch register (P8SPR) [Address:34 16]
B
Name
switch register
Function
0 : Port P80 for I/O 1 : SEG8 0 : Port P81 for I/O 1 : SEG9 0 : Port P82 for I/O 1 : SEG10 0 : Port P83 for I/O 1 : SEG11 0 : Port P84 for I/O 1 : SEG12 0 : Port P85 for I/O 1 : SEG13 0 : Port P86 for I/O 1 : SEG14 0 : Port P87 for I/O 1 : SEG15
At reset
RW
0 Port P8 segment/port 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 2.5.3 Structure of Port P8 segment/port switch register
Port PA segment/port switch register
b7 b6 b5 b4 b3 b2 b1 b0 Port PA segment/port switch register (PASPR) [Address:3516]
B
Name
switch register
Function
0 : Port PA0 for I/O 1 : SEG0 0 : Port PA1 for I/O 1 : SEG1 0 : Port PA2 for I/O 1 : SEG2 0 : Port PA3 for I/O 1 : SEG3 0 : Port PA4 for I/O 1 : SEG4 0 : Port PA5 for I/O 1 : SEG5 0 : Port PA6 for I/O 1 : SEG6 0 : Port PA7 for I/O 1 : SEG7
At reset
RW
0 Port PA segment/port 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 2.5.4 Structure of Port PA segment/port switch register
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3819 Group 2.5 FLD controller
FLDC mode register 1
b7 b6 b5 b4 b3 b2 b1 b0 FLDC mode register 1 (FLDM1) [Address:3616]
B
Name
b1b0
Function
0 0 : FLD digit interrupt (at rising edge of each digit) 0 1 : 1 ! Tdisp 1 0 : 2 ! Tdisp FLD blanking 1 1 : 3 ! Tdisp interrupt (at falling edge of the last digit)
b5 b4 b3 b2
At reset
RW
0 Tscan control bits
0
1
0 0
2 Toff control bit
3
4
5
6 7
0 0 0 0 : 1/16 ! Tdisp 0 0 0 1 : 2/16 ! Tdisp 0 0 1 0 : 3/16 ! Tdisp 0 0 1 1 : 4/16 ! Tdisp 0 1 0 0 : 5/16 ! Tdisp 0 1 0 1 : 6/16 ! Tdisp 0 1 1 0 : 7/16 ! Tdisp 0 1 1 1 : 8/16 ! Tdisp 1 0 0 0 : 9/16 ! Tdisp 1 0 0 1 : 10/16 ! Tdisp 1 0 1 0 : 11/16 ! Tdisp 1 0 1 1 : 12/16 ! Tdisp 1 1 0 0 : 13/16 ! Tdisp 1 1 0 1 : 14/16 ! Tdisp 1 1 1 0 : 15/16 ! Tdisp 1 1 1 1 : 16/16 ! Tdisp Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0." 0 : Strong drivability High-breakdown-voltage 1 : Weak drivability drivability selection bit (Setting of digit/segment OFF time)
0
0
0
0 0
!
Fig. 2.5.5 Structure of FLDC mode register 1
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3819 Group 2.5 FLD controller
FLDC mode register 2
b7 b6 b5 b4 b3 b2 b1 b0 FLDC mode register 2 (FLDM2) [Address:3716]
B
Name
Function
At reset
RW
0 Automatic display control bit 1 Display start bit
0 : Ordinary mode (P0,P1,P20-P23,P3,P8,P9,PA) 1 : Automatic display mode 0 : Display stopped 1 : Display in progress (display starts by writing "1" to this bit which is set to "0".)
b5 b4 b3 b2
0 0
2
3
Tdisp control bits (digit time setting) (at 8 MHz oscillation frequency)
4
5
0 0 0 0 : 128 s 0 0 0 1 : 256 s 0 0 1 0 : 384 s 0 0 1 1 : 512 s 0 1 0 0 : 640 s 0 1 0 1 : 768 s 0 1 1 0 : 896 s 0 1 1 1 : 1024 s 1 0 0 0 : 1152 s 1 0 0 1 : 1280 s 1010 Not available 1111
0
0
0
0
6 P10 segment/digit switch bit 7 P11 segment/digit switch bit
0 : Digit (DIG8) 1 : Segment (SEG 40) 0 : Digit (DIG9) 1 : Segment (SEG 41)
....
0 0
Fig. 2.5.6 Structure of FLDC mode register 2
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3819 Group 2.5 FLD controller
FLD data pointer
b7 b6 b5 b4 b3 b2 b1 b0 FLD data pointer (FLDDP) [Address:38 16]
B
Function
the FLD automatic display RAM.
At reset
RW
! ! ! ! ! ! ! !
0 Indicate the address of data which is transfered to the segment of 1 2 3 4 5 6 7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0."
? ? ? ? ? ? ? 0
Fig. 2.5.7 Structure of FLD data pointer
FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0 FLD data pointer reload register (FLDDP) [Address:38 16]
B
Function
At reset
RW
! ! ! ! ! ! ! !!
0 Indicate the first digit address of the high-order segment. 1 2 3 4 5 6 7 Nothing is allocated for this bit. This is a write disabled bit.
? ? ? ? ? ? ? ?
Fig. 2.5.8 Structure of FLD data pointer reload register
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3819 Group 2.5 FLD controller
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address:3D16]
b
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T
0 Timer 3 interrupt request bit 1 Timer 4 interrupt request bit 2 Timer 5 interrupt request bit 3 Timer 6 interrupt request bit 4 INT3 interrupt request bit 5
q q
0 0 0 0 0 0
INT4 interrupt request bit A-D conversion interrupt request bit
6
q
q
FLD blanking interrupt 0 : No interrupt request request bit 1 : Interrupt request FLD digit interrupt request bit
0
T
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0." T "0" is set by software, but not "1."
0
T
Fig. 2.5.9 Structure of Interrupt request register 2
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address:3F16]
b
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 Timer 3 interrupt enable bit 1 Timer 4 interrupt enable bit 2 Timer 5 interrupt enable bit 3 Timer 6 interrupt enable bit 4 INT3 interrupt enable bit 5
q q
0 0 0 0 0 0
INT4 interrupt enable bit A-D conversion interrupt enable bit FLD blanking interrupt enable bit FLD digit interrupt enable bit
6
q
0 0
q
7 Fix this bit to "0."
Fig. 2.5.10 Structure of Interrupt control register 2
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2.5.2 FLD controller application examples (1) FLD automatic display and Key-scan using segment pin
3819 Group 2.5 FLD controller
Outline : The pannel with fluorescent display (FLD) is displayed by using FLD automatic display function. Then the key is read in with using segment pin by software.
P02-P07 P10-P13 P00,P01 P30-P37 P24-P27 3819 group
digit SP LP segment segment
LEVEL L R
SUN MON TUE WED THU FRI SAT REC
AM PM CH
Key matrix
Pannel with fluorescent display (FLD)
Fig. 2.5.11 Connection diagram [FLD automatic display and Key-scan using segment pin] Specifications : * The automatic display function is used. * 10 digits and 10 segments are used. * Toff = 15.27 s, Tdisp = 244.39 s, Tscan = 733.17 s (at f(XIN) = 4.19 MHz) * The FLD blanking interrupt is used. * The segment pin is used for the Key-scan. Figure 2.5.12 shows a timing chart of the Key-scan using an FLD automatic display and segments, and Figure 2.5.13 shows an enlarged view of SEG24 to SEG31 during Tscan.
Tdisp DIG2(P02)
Tscan
DIG3(P03)
DIG4(P04)
qqqq qqqq
DIG11(P13) FLD blanking interrupt request occurs SEG24-SEG33 (P30-P37,P00,P01)
qqqq
Key-scan
Fig. 2.5.12 Timing chart [FLD automatic display and Key-scan using segment pin]
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3819 Group 2.5 FLD controller
After switching a segment pin to an output port, the waveform shown below is created by software, and the Key-scan is performed.
SEG24 (P30) SEG25 (P31) SEG26 (P32) SEG31 (P37)
qqq
qqq
Fig. 2.5.13 Enlarged view of SEG24 to SEG31 during Tscan Figures 2.5.14 and 2.5.15 show a setting of related registers.
FLDC mode register 2 (Address:3716) FLDM2 00000001
Automatic display mode Stop displaying Tdisp = 244.39 s Set ports P11 and P10 to digit (DIG9, DIG8)
FLDC mode register 1 (Address:3616) FLDM1 1 000011
Tscan = 3 ! Tdisp = 733.17 s Toff = 1/16!Tdisp = 15.27 s Dull the output waveform of the High-breakdown-voltage port
FLD data pointer (Address:3816) FLDDP 0001001
Set the value of "the number of digits - 1"
Fig. 2.5.14 Setting of related registers (1) [FLD automatic display and Key-scan using segment pin]
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3819 Group 2.5 FLD controller
Port P0 segment/digit switch register (Address:3216) P0SDR 00000011
Set ports P01 and P00 to segment (SEG33, SEG32) Set ports P07-P02 to digit (DIG7-DIG2)
Port P2 digit/port switch register (Address:3316) P2DPR 0000
Set ports P23-P20 to output-only port
Port P8 segment/port switch register (Address:3416) P8SPR 00000000
Set ports P87-P80 to I/O port
Port PA segment/port switch register (Address:3516) PASPR 00000000
Set ports PA7-PA0 to I/O port
Port P2 direction register (Address:0516) P2D 0000
Set ports P27-P24 to the input mode
Interrupt request register 2 (Address:3D16) IREQ2 0
Set the FLD blanking interrupt request bit to "0".
Interrupt control register 2 (Address:3F16) ICON2 01
FLD blanking interrupt : Enabled
FLDC mode register 2 (Address:3716) FLDM2 00000011
Start displaying
Fig. 2.5.15 Setting of related registers (2) [FLD automatic display and Key-scan using segment pin]
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Setting of FLD automatic display RAM :
3819 Group 2.5 FLD controller
Table 2.5.1 FLD automatic display RAM map [FLD automatic display and Key-scan using segment pin]
Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 Bit 7 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 Bit 6 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 Bit 5 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 Bit 4 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 Bit 3 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 Bit 2 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 Bit 1 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 Bit 0 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24
DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG3 (P03) DIG2 (P02)
SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33
: Area which is used to set a display value : Area which is available as ordinary RAM
SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32
DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG3 (P03) DIG2 (P02)
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FLD digit allocation :
3819 Group 2.5 FLD controller
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
DIG10
DIG11
SUN MON TUE WED THU FRI SAT
SP LP REC
AM PM CH
a f
L R DIG3 DIG2
g
b c
e d
LEVEL
Fig. 2.5.16 Example of FLD digit allocation [FLD automatic display and Key-scan using segment pin] Table 2.5.2 FLD automatic display RAM map example [FLD automatic display and Key-scan using segment pin]
Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 Bit 7 CH SAT FRI WED MON SUN -- Bit 6 g g g g g g g Bit 5 f f f f f f f Bit 4 e e e e e e e Bit 3 d d d d d d d Bit 2 c c c c c c c
REC
Bit 1 b b b b b b b
SP
Bit 0 a a a a a a a
LP
DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG3 (P03) DIG2 (P02)
DIG11 (P13)
PM
AM THU TUE
DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04)
L R LEVEL : Unused
DIG3 (P03) DIG2 (P02)
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Control procedure : Figure 2.5.17 shows a control procedure.
3819 Group 2.5 FLD controller
RESET
Initialization FLDM1 FLDM2 FLDDP P0SDR P2DPR P8SPR PASPR P2D
FLD automatic display RAM (Address:0FB016 to 0FC916)
Main processing Note : The display data is re-written at any time.
Fig. 2.5.17 Control procedure [FLD automatic display and Key-scan using segment pin]
....
(Address:3616) (Address:3716) (Address:3816) (Address:3216) (Address:3316) (Address:3416) (Address:3516) (Address:0516) 100000112 000000012 000010012 000000112 000000002 000000002 000000002 000000002
q
Set related functions for using the FLD automatic display. Set segment/digit /port. Set the bits 7 to 4 of the Port P2 direction register used for the Key-scan to input mode.
q
q
....
q
a data to be displayed
q
To turn on the display of the corresponding segment : set to "1" To turn off the display of the corresponding segment : set to "0" ( Note) Set the FLD blanking interrupt request bit to "0".
q
IREQ2 (Address:3D 16), bit6
0 Wait until completing to write data to the FLD blanking interrupt request bit.
q
Wait for 1 or more cycles
q
ICON2 (Address:3F 16) , bit6 FLDM2 (Address:37 16), bit1
1 1
q
FLD blanking interrupt : Enabled Start the FLD automatic display.
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Segment key-scan (FLD blanking interrupt) :
3819 Group 2.5 FLD controller
FLD blanking interrupt processing routine Push register to stack etc. FLDM2(Address:3716), bit0 (Address:0216), bit0-bit3 P1 (Address:0016) P0 (Address:0616) P3
.... ....
q
Segment key-scan
0 00002 0016 0016
q
Switch the FLD automatic display pin to the ordinary port.
Set data table for Key-scan to P3 (Address:06 16)
Wait for Key-scan
q
Wait until the "H" level output of port P3 i is stabilized.
T
Transfer the contents of P2 (Address:0416) to Work RAM
q
Read keys. (Set the Port P2 direction register (P2D) (Address:0516) to input mode in the initialization.) Renew the data table reference pointer for the next Key-scan.
Renew data table pointer for Key-scan
q
N
Complete Key-scan?( Note) Y Set Key-scan completion flag Initialize data table pointer for Key-scan Set the flag for checking if the Key-scan has been completed.
q
(Address:0616) P3 (Address:0016) P0 FLDM2 (Address:3716), bit0
0016 0016 1
q
Output "L" level from all Key-scan ports. Switch the FLD automatic display pin to the automatic display mode. Note : When the Key-scan is not completed within the Tscan setting time, it is divided and performed T i = 0 to 7
q
~ ~
RTI
Fig. 2.5.18 Control procedure of Segment key-scan
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(2) FLD automatic display and Key-scan using digit pin
3819 Group 2.5 FLD controller
Outline : The pannel with fluorescent display (FLD) is displayed by using FLD automatic display function. Then the key is read in with using digit output waveforms.
P30-P37 P00,P01 P02-P07 P10-P13 P24-P27 3819 group
segment segment digit SP LP REC
SUN MON TUE WED THU FRI SAT
AM PM
CH
LEVEL
L R
Key matrix
Pannel with fluorescent display (FLD)
Fig. 2.5.19 Connection diagram [FLD automatic display and Key-scan using digit pin] Specifications : * The automatic display function is used. * 10 digits and 10 segments are used. * Toff = 15.27 s, Tdisp = 244.39 s, Tscan = 0 s (at f(XIN) = 4.19 MHz) * The FLD digit interrupt is used. * The digit pin is used for the Key-scan.
Tdisp DIG2(P02) FLD digit interrupt request occurs DIG3(P03)
Tscan = 0 s
FLD digit interrupt request occurs DIG4(P04) FLD digit interrupt request occurs
qqqq qqqq
DIG11(P13) FLD digit interrupt request occurs SEG24-SEG33 (P30-P37,P00,P01)
qqqq
Fig. 2.5.20 Timing chart [FLD automatic display and Key-scan using digit pin]
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3819 Group 2.5 FLD controller
FLDC mode register 1 (Address:3616) FLDM1 1 000000
Tscan = 0 s Toff = 1/16!Tdisp = 15.27 s Dull the output waveform of the High-breakdown-voltage port
FLDC mode register 2 (Address:3716) FLDM2 00000001
Automatic display mode Stop displaying Tdisp = 244.39 s Set ports P11 and P10 to digit (DIG9, DIG8)
FLD data pointer (Address:3816) FLDDP 0001001
Set the value of "the number of digits - 1"
Port P0 segment/digit switch register (Address:3216) P0SDR 00000011
Set ports P01 and P00 to segment (SEG 33, SEG32) Set ports P07-P02 to digit (DIG7-DIG2)
Port P2 digit/port switch register (Address:33 16) P2DPR 0000
Set ports P23-P20 to output-only port
Port P8 segment/port switch register (Address:3416) P8SPR 00000000
Set ports P87-P80 to I/O port
Fig. 2.5.21 Setting of related registers (1) [FLD automatic display and Key-scan using digit pin]
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3819 Group 2.5 FLD controller
Port PA segment/port switch register (Address:3516) PASPR 00000000
Set ports PA7-PA0 to ordinary port
Port P2 direction register (Address:0516) P2D 0000
Set ports P27-P24 to the input mode
Interrupt request register 2 (Address:3D16) IREQ2 0
Set the FLD digit interrupt request bit to "0"
Interrupt control register 2 (Address:3F16) ICON2 01
FLD digit interrupt : Enabled
FLDC mode register 2 (Address:3716) FLDM2 00000011
Start displaying
Fig. 2.5.22 Setting of related registers (2) [FLD automatic display and Key-scan using digit pin]
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Setting of FLD automatic display RAM :
3819 Group 2.5 FLD controller
Table 2.5.3 FLD automatic display RAM map [FLD automatic display and Key-scan using digit pin]
Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 Bit 7 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 Bit 6 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 Bit 5 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 Bit 4 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 Bit 3 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 Bit 2 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 Bit 1 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 Bit 0 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24
DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG3 (P03) DIG2 (P02)
SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33
: Area which is used to set a display value : Area which is available as ordinary RAM
SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32
DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG3 (P03) DIG2 (P02)
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FLD digit allocation :
3819 Group 2.5 FLD controller
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
DIG10
DIG11
SUN MON TUE WED THU FRI SAT
SP LP REC
AM PM CH
a f
DIG3 DIG2
g
b c
LEVEL
L R
e d
Fig. 2.5.23 Example of FLD digit allocation [FLD automatic display and Key-scan using digit pin] Table 2.5.4 FLD automatic display RAM map example [FLD automatic display and Key-scan using digit pin] Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 Bit 7 CH SAT FRI WED MON SUN -- Bit 6 g g g g g g g Bit 5 f f f f f f f Bit 4 e e e e e e e Bit 3 d d d d d d d Bit 2 c c c c c c c
REC
Bit 1 b b b b b b b
SP
Bit 0 a a a a a a a
LP
DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG3 (P03) DIG2 (P02)
DIG11 (P13)
PM
AM THU TUE
DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04)
L R LEVEL : Unused
DIG3 (P03) DIG2 (P02)
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Control procedure : Figure 2.5.24 shows a control procedure.
3819 Group 2.5 FLD controller
RESET
Initialization FLDM1 FLDM2 FLDDP P0SDR P2DPR P8SPR PASPR P2D
FLD automatic display RAM (Address:0FB016 to 0FC916)
Fig. 2.5.24 Control procedure [FLD automatic display and Key-scan using digit pin]
....
(Address:3616) (Address:3716) (Address:3816) (Address:3216) (Address:3316) (Address:3416) (Address:3516) (Address:0516) 100000002 000000012 000010012 000000112 000000002 000000002 000000002 000000002
q
Set the related functions for the FLD automatic display. Set segment/digit/port.
q
q
Set the bits 7 to 4 of the Port P2 direction register used for the Key- scan to the input mode.
....
a data to be displayed
q q
To turn on the display of the corresponding segment : set to "1" To turn off the display of the corresponding segment : set to "0" ( Note) Set the FLD digit interrupt request bit to "0".
IREQ2 (Address:3D 16), bit6
0
q
q
Wait for 1 or more cycles
Wait until completing to write data to the FLD digit interrupt request bit.
ICON2 (Address:3F 16) , bit6 FLDM2 (Address:37 16) , bit1
1 1
q q
FLD digit interrupt : Enabled Start the FLD automatic display. Note : The display data is rewritten at any time.
~ ~
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Digit key-scan (FLD digit interrupt) :
3819 Group 2.5 FLD controller
FLD digit interrupt processing routine
q
Digit key-scan
Push register to stack etc. ....
q
Wait for Key-scan
Wait until the digit output is stabilized since the digit output waveform may dull because of the printed circuit board (PCB) pattern wiring length or other factors. Read keys. (Set the Port P2 direction register (P2D) (Address:0516) to the input mode in the initialization.)
Transfer the contents of P2 (Address:0416) to Work RAM
q
Store the contents of Work RAM into buffer
~ ~
RTI
Fig. 2.5.25 Control procedure of Digit key-scan
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(3) FLD display by software (example of without using FLD controller)
3819 Group 2.5 FLD controller
Outline : The FLD display and the key read-in are performed by using timer interrupts.
P02-P07 P10-P13 P00,P01 P30-P37 P24-P27 3819 group
digit SP LP segment segment
LEVEL L R
SUN MON TUE WED THU FRI SAT REC
AM PM CH
Key matrix
Pannel with fluorescent display (FLD)
Fig. 2.5.26 Connection diagram [FLD display by software] Specifications : * The display is controlled by software. * 10 digits and 10 segments are used. * The Timer 1 interrupts are used. * The segment pin is used for Key-scan. Fig. 2.5.27 shows a timing chart of FLD display by software, and Fig. 2.5.28 shows an enlarged view of Key-scan of ports P30 to P37.
P02 P03
P04
qqqq qqqq
P13 P30-P37, P00,P01
qqqq
Key-scan
Fig. 2.5.27 Timing chart [FLD display by software]
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3819 Group 2.5 FLD controller
The waveform shown below is created by software, and the Key-scan is performed.
P30 P31 P32 P37
qqq
qqq
Fig. 2.5.28 Enlarged view of Key-scan of ports P30 to P37 Figure 2.5.29 shows a setting of related registers.
FLDC mode register 2 (Address:3716) FLDM2 00
Ordinary mode Stop displaying
FLDC mode register 1 (Address:3616) FLDM1 1
Dull the output waveform of the High-breakdown-voltage port
Port P2 direction register (Address:0516) P2D 0000
Set ports P27-P24 to the input mode
Fig. 2.5.29 Setting of related registers [FLD display by software]
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FLD digit allocation :
3819 Group 2.5 FLD controller
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
DIG10
DIG11
SUN MON TUE WED THU FRI SAT
SP LP REC
AM PM CH
a f
L R DIG3 DIG2
g
b c
e d
LEVEL
Fig. 2.5.30 Example of FLD digit allocation [FLD display by software] Table 2.5.5 FLD automatic display RAM map example [FLD display by software] (Automatic display is not performed because of not using FLD controller)
Address 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916
Bit 7 CH SAT FRI WED MON SUN --
Bit 6 g g g g g g g
Bit 5 f f f f f f f
Bit 4 e e e e e e e
Bit 3 d d d d d d d
Bit 2 c c c c c c c
REC
Bit 1 b b b b b b b
SP
Bit 0 a a a a a a a
LP
DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG3 (P03) DIG2 (P02)
DIG11 (P13)
PM
AM THU TUE
DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04)
L R LEVEL : Unused
DIG3 (P03) DIG2 (P02)
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Control procedure : Figure 2.5.31 shows a control procedure.
3819 Group 2.5 FLD controller
RESET Initialization FLDM1 (Address:3616), bit7 1 FLDM2 (Address:3716), bit1, bit0 002 (Address:0516) P2D 000000002
.... ....
q
Set the bits 7 to 4 of the Port P2 direction register used for the Key-scan to the input mode.
~ ~
Timer 1 interrupt processing routine Push register to stack etc. P0 (Address:0016) P1 (Address:0216), bit0-bit3 P3 (Address:0616)
.... ....
q
Segment key-scan
0016 00002 0016
q
FLD display : OFF
Complete to display all digits? Y Set data table for Key-scan to port P3 (Address:06 16) Wait until the "H" level output of port P3 is stabilized.
N P0 (Address:00 16), bit0, bit1 P3 (Address:06 16) segment data
P0 (Address:0016),bit2-bit7 P1 (Address:0216),bit0-bit3 Wait for Key-scan
digit data
Transfer the contents of port P2 (Address:0416) to Work RAM
q
Read keys. (Set the Port P2 direction register (P2D) (Address:0516) to the input mode in the initialization.)
~ ~
Renew data table pointer for Key-scan
N
Complete Key-scan? Y
~ ~
RTI
Fig. 2.5.31 Control procedure [FLD display by software]
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(4) 5 ! 7 dot display
3819 Group 2.5 FLD controller
Outline : The 5 ! 7 dot display is performed by using the FLD automatic display function.
SEG0-SEG34 DIG4-DIG19
35 segments 16 digits
3819 group
Fig. 2.5.32 Connection diagram [5 ! 7 dot display] Specifications : * The automatic display function is used. * 16 digits and 35 segments are used. * Toff = 288 s, Tdisp = 512 s, Tscan = 512 s (at f(XIN) = 8 MHz) Figure 2.5.33 shows a timing chart of FLD automatic display.
DIG4 (P04) DIG5 (P05)
DIG6 (P06)
qqqq qqqq
DIG19 (P23) SEG0-SEG35 (PA0-PA7, P80-P87, P90-P97, P30-P37, P00-P02)
qqqq
Fig. 2.5.33 Timing chart [5 ! 7 dot display]
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Figures 2.5.34 and 2.5.35 show a setting of related registers.
3819 Group 2.5 FLD controller
FLDC mode register 1 (Address:3616) FLDM1 0 100000
Tscan = 512 s Toff = 9/16 ! Tdisp = 288 s High-breakdown-voltage port drivability : Strong
FLDC mode register 2 (Address:3716) FLDM2 00001101
Automatic display mode Stop displaying Tdisp = 512 s Set ports P11 and P10 to digit (DIG9, DIG8)
Port P0 segment/digit switch register (Address:32 16) P0SDR 00001111
Set ports P03-P00 to segment (SEG 35-SEG32) (However, SEG 35 is unused.) Set ports P07-P04 to digit (DIG7-DIG4)
Port P2 digit/port switch register (Address:3316) P2DPR 1111
Set ports P23-P20 to digit (DIG19-DIG16)
Fig. 2.5.34 Setting of related registers (1) [5 ! 7 dot display]
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3819 Group 2.5 FLD controller
Port P8 segment/port switch register (Address:3416) P8SPR 11111111
Set ports P87-P80 to segment (SEG15-SEG8)
Port PA segment/port switch register (Address:3516) PASPR 11111111
Set ports PA7-PA0 to segment (SEG7-SEG0 )
FLD data pointer reload register (Address:3816) FLDDP 0001111
Set the value of "the number of digits - 1"
FLDC mode register 2 (Address:3716) FLDM2 00001111
Start displaying
Fig. 2.5.35 Setting of related registers (2) [5 ! 7 dot display]
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Setting of FLD automatic display RAM : Table 2.5.6 FLD automatic display RAM map [5 ! 7 dot display]
3819 Group 2.5 FLD controller
Address
0F8016 0F8116 0F8216 0F8316 0F8416 0F8516 0F8616 0F8716 0F8816 0F8916 0F8A16 0F8B16 0F8C16 0F8D16 0F8E16 0F8F16 0F9016 0F9116 0F9216 0F9316 0F9416 0F9516 0F9616 0F9716 0F9816 0F9916 0F9A16 0F9B16 0F9C16 0F9D16 0F9E16 0F9F16 0FA016 0FA116 0FA216 0FA316 0FA416 0FA516 0FA616 0FA716 0FA816 0FA916 0FAA16 0FAB16 0FAC16 0FAD16 0FAE16 0FAF16 0FB016 0FB116 0FB216 0FB316 0FB416 0FB516 0FB616 0FB716 0FB816 0FB916 0FBA16 0FBB16 0FBC16 0FBD16 0FBE16 0FBF16 0FC016 0FC116 0FC216 0FC316 0FC416 0FC516 0FC616 0FC716 0FC816 0FC916 0FCA16 0FCB16 0FCC16 0FCD16 0FCE16 0FCF16
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIG19 (P23) DIG18 (P22) DIG17 (P21) DIG16 (P20) DIG15 (P17) DIG14 (P16) DIG13 (P15) DIG12 (P14) DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG19 (P23) DIG18 (P22) DIG17 (P21) DIG16 (P20) DIG15 (P17) DIG14 (P16) DIG13 (P15) DIG12 (P14) DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG19 (P23) DIG18 (P22) DIG17 (P21) DIG16 (P20) DIG15 (P17) DIG14 (P16) DIG13 (P15) DIG12 (P14) DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG19 (P23) DIG18 (P22) DIG17 (P21) DIG16 (P20) DIG15 (P17) DIG14 (P16) DIG13 (P15) DIG12 (P14) DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04) DIG19 (P23) DIG18 (P22) DIG17 (P21) DIG16 (P20) DIG15 (P17) DIG14 (P16) DIG13 (P15) DIG12 (P14) DIG11 (P13) DIG10 (P12) DIG9 (P11) DIG8 (P10) DIG7 (P07) DIG6 (P06) DIG5 (P05) DIG4 (P04)
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG34
SEG33
SEG32
: Area which is used to set a display value : Area which is available as ordinary RAM
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FLD digit allocation :
3819 Group 2.5 FLD controller
DIG4
DIG5
DIG6
DIG7
DIG8
DIG9
DIG10 DIG11 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
DIG12 DIG13 DIG14 DIG15 DIG16
DIG17 DIG18
DIG19
SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34
Fig. 2.5.36 Example of FLD digit allocation and segment arrangment Setting example of display data (in case of using DIG11) :
DIG11
Address
0F8016 0F8516 0F8616 0F8716 0F9516 0F9616 0F9716 0FA516 0FA616 0FA716 0FB516 0FB616 0FB716 0FBF16 0FC016 0FC516 0FC616 0FC716 0FCF16
q q q q q q q q q q q q q q q q q q q q q
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0

0 1 0
Fig. 2.5.37 Setting example of display data (in case of using DIG11 pin)
0 0 0
0 0 0
0 0 0
0 0 0
0 1 0
0 0 0
0 0 0
DIG11 (P14)

0 1 0
0 1 0
0 0 0
0 0 0
0 0 0
0 1 0
0 0 0
0 1 0
DIG11 (P14)

0 0 0
0 0 0
0 0 0
0 1 0
0 1 0
0 1 0
0 1 0
0 1 0
DIG11 (P14)

0 1 0
0 0 0
0 1 0
0 0 0
0 0 0
0 0 0
0 1 0
0 1 0
DIG11 (P14)

0
0
0
0
0
0 1
0 0
0 0
3819 Group USER'S MANUAL
0 1 0
0 0 0
0 0 0
DIG11 (P14)
0
0 : Unused
0
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Control procedure : Figure 2.5.38 shows a control procedure.
3819 Group 2.5 FLD controller
RESET
Initialization FLDM1 FLDM2 P0SDR P2DPR P8SPR PASPR FLDDP
FLD automatic display RAM (Address:0F8016 to 0FCF16)
FLDM2 (Address:37 16), bit1
Fig. 2.5.38 Control procedure [5 ! 7 dot display]
....
(Address:3616) (Address:3716) (Address:3216) (Address:3316) (Address:3416) (Address:3516) (Address:3816)
001000012 000011012 000011112 000011112 111111112 111111112 000011112
q
Set the related functions for using the FLD automatic display. Set segment/digit/port.
q
....
a data to be displayed
q
q
To turn on the display of the corresponding segment : set to "1" To turn off the display of the corresponding segment : set to "0" ( Note) Start the FLD automatic dislay
1
q
~ ~
Note : The display data is rewritten at any time.
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3819 Group 2.6 Interrupt interval determination function
2.6 Interrupt interval determination function
2.6.1 Related registers
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt interval determination register (IID) [Address:3016]
B 0 1 2 3 4 5 6 7
Function
This register stores the values obtaind by counting the following interval with a counter sampling clock. Falling edge interval Rising edge interval Both-sided edge interval (selected by the interrupt edge selection register) This register is read-only.
q q q
At reset
RW
! ! ! ! ! ! ! !
? ? ? ? ? ? ? ?
Note : When the noise filter sampling clock selection bits (bits 2 and 3) of the Interrupt interval determination control register (IIDCON) (Address: 31 16) is set to "00" (when no noise filter is used), the both-sided edge detection function is not available.
Fig. 2.6.1 Structure of Interrupt interval determination register
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt interval determination control register (IIDCON) [Address:3116]
B
Name
Function
0 : Stopped 1 : Operating 0 : f(XIN)/256 1 : f(XIN)/512 00 : Filter stop 01 : f(XIN)/64 10 : f(XIN)/128 11 : f(XIN)/256
At reset
RW
0 Interrupt interval determination circuit operating selection bit 1 Counter sampling clock selection bit 2 Noise filter sampling clock
selection bits (INT 2)
0 0 0 0 0 0 0 0
! ! !
3 4 One-sided/both-sided edge
0 : One-sided edge detection 1 : Both-sided edge detection (Note) detection selection bit 5 Nothing is allocated for these bits. These are write disabled bits. 6 When these bits are read out, the values are "0."
7
Note : When the noise filter sampling clock selection bits (bits 2 and 3) of the Interrupt interval determination control register (IIDCON) (Address: 31 16) is set to "00" (when no noise filter is used), the both-sided edge detection function is not available.
Fig. 2.6.2 Structure of Interrupt interval determination control register
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3819 Group 2.6 Interrupt interval determination function
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selecton reigster (INTEDGE) [Address:3A16]
b 0 1 2 3 4 5 6 7
Name
Function
At reset
RW
0 : Falling edge active INT0 interrupt edge selection 1 : Rising edge active bit 0 : Falling edge active INT1/ZCR interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT2 interrupt edge selection 1 : Rising edge active bit 0 : Falling edge active INT3 interrupt edge selection 1 : Rising edge active bit 0 : Falling edge active INT4 interrupt edge selection 1 : Rising edge active bit INT4/A-D conversion interrupt 0 : INT4 interrupt 1 : A-D conversion interrupt switch bit CNTR0 pin active edge switch 0 : Falling edge active 1 : Rising edge active bit CNTR1 pin active edge switch 0 : Falling edge active 1 : Rising edge active bit
0 0 0 0 0 0 0 0
Fig. 2.6.3 Structure of Interrupt edge selection register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address:3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T
0 INT0 interrupt request bit 1 INT1/ZCR interrupt request bit 2
INT2 interrupt request bit Remote control/counter overflow interrupt request bit 3 q Serial I/O 1 interrupt request bit q Serial I/O automatic transfer interrupt request bit
q q
0 0 0
0
T
4 Serial I/O 2 interrupt request
bit 5 Serial I/O 3 interrupt request bit 6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
0 0 0 0
T T T T
T "0" is set by software, but not "1."
Fig. 2.6.4 Structure of Interrupt request register 1
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3819 Group 2.6 Interrupt interval determination function
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address:3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1/ZCR interrupt enable bit 2
q q
0 0 0
INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit
3
Serial I/O 1 interrupt enable bit q Serial I/O automatic transfer interrupt enable bit
q
0
4 Serial I/O 2 interrupt enable
bit Serial I/O 3 interrupt enable 5 bit Timer 1 interrupt enable bit 6
7 Timer 2 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
Fig. 2.6.5 Structure of Interrupt control register 1
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3819 Group 2.6 Interrupt interval determination function
2.6.2 Interrupt interval determination function Reception of remote-control signal Outline : Remote-control signal is read in by both of the interrupt interval determination function using a noise filter and a timer interrupt.
P42/INT2
Reciever unit Remote-control
3819 group
Fig. 2.6.6 Connection diagram [Reception of remote-control signal] Specifications : * Operation at f(XIN) = 8 MHz in the high-speed mode. * The one-sided edge interval is measured. * The noise filter is used. * The remote control interrupt request is checked within the timer 2 interrupt (488 s cycle) processing routine. Figure 2.6.7 shows a function block diagram, and Figure 2.6.8 shows a timing chart of data determination.
Microcomputer hardware Reciever unit Noise filter
* Eliminate noise * One-sided edge Interrupt interval determination register * One-sided edge
Microcomputer software
Determination of header or 0/1 * Read out a register * Compare the readout
1-byte reception
Data check
* Recognition of
interval judgment
each code
detection
value with the reference value
Fig. 2.6.7 Function block diagram [Reception of remote-control signal]
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3819 Group 2.6 Interrupt interval determination function
Input (INT2) (Overflow) Interrupt request
(R) (R) (R) (R) (R) (R) (R) (R)
Timer interrupt (488 s) Read interrupt interval determination register
Data determination
Ignore
Fig. 2.6.8 Timing chart of data determination

(R) (R) (R)
~ ~
Header
0
1
1
Check of an excess bit
~ ~
(R)
3819 Group USER'S MANUAL
(R)
(R)
Ignore Ignore
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3819 Group 2.6 Interrupt interval determination function
Figure 2.6.9 shows a setting of related registers.
CPU mode register (Address:3B16) CPUM 0
Main clock division ratio : select the high-speed mode.
Interrupt edge selection register (Address:3A16) INTEDGE 0
INT2 pin : Falling edge active
Interrupt interval determination control register (Address:3116) IIDCON 10111
Interrupt interval determination circuit operating Counter sampling clock : f(XIN)/512 Noise filter sampling clock : f(XIN)/128 One-sided edge detection
Interrupt request register 1 (Address:3C16) IREQ1 1
Determination of the remote-control interrupt request bit (Counter overflow interrupt request bit)
Interrupt control register 1 (Address:3E16) ICON1 0
Remote-control interrupt : Disabled (Counter overflow interrupt : Disabled)
Interrupt interval determination register (Address:3016) IID
Determine header or data (0 or 1) with this value
Fig. 2.6.9 Setting of related registers [Reception of remote-control signal]
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3819 Group 2.6 Interrupt interval determination function
Control procedure : When the registers are set as shown in Figure 2.6.9, remote-control signals are receivable. Figure 2.6.10 shows a control procedure and Figure 2.6.11 shows reception of remote-control signal (Timer 2 interrupt).
RESET Initialization SEI (Address:3B16), bit6 CPUM 0 INTEDGE (Address:3A16), bit2 0 IIDCON (Address:3116) 000101112 (Address:3C16), bit2 IREQ1 0 NOP (Address:3E16), bit2 ICON1 0 CLI
.... ....
~ ~
Fig. 2.6.10 Control procedure (1) [Reception of remote-control signal]
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3819 Group 2.6 Interrupt interval determination function
Timer 2 interrupt
Push register to stack etc.
Input edge? Y Clear edge
N
During checking an excess bit? Y
N
Y
During checking an excess bit? N
An excess bit determined counter over? Y
N
"Number of bits" error (An excess bit is found) RTI Y
Read IID (Address : 0030 16) Fixed data
IID (Address : 0030 16) = FF? N In range of header? Y
RTI
Time error
RTI N Out of range of 0 or 1 In range of data, 0 or 1? In range of 1 CY RTI Shift a reception data 1 CY 0 Starting to receive a data etc. In range of 0 RTI Time error
Complete to receive? Y Start chacking an excess bit
N
RTI
Fig. 2.6.11 Control procedure (2) [Reception of remote-control signal] (Timer 2 interrupt)
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2.7 Zero cross detection circuit
2.7.1 Related registers
3819 Group 2.7 Zero cross detection circuit
Zero cross detection control register
b7 b6 b5 b4 b3 b2 b1 b0 Zero cross detection control register (ZCRCON) [Address:3916]
B
Name
selection bit
Function
0 : Without passing through zero cross detection comparator 1 : Passing through zero cross detection comparator
At reset
RW
0 Zero cross detection ON/OFF
0
1 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is "0."
0 0 0 0 0 0
!
2 Noise filter sampling
clock selection bits 3 (INT1)
4 One-sided/both-sided edge
detection selection bit 5 Nothing is allocated for these bits. These are write disabled bits. 6 When these bits are read out, the values are "0." 0 : Less than 0 V 7 Zero cross detection circuit input bit (read-only) 1 : 0 V or more
00 : Note use noise filter 01 : f(XIN)/64 or f(XCIN)/64 10 : f(XIN)/128 or f(XCIN)/128 11 : f(XIN)/256 or f(XCIN)/256 0 : One-sided edge detection 1 : Both-sided edges detection ( Note)
b3 b2
! ! !
Note : When the noise filter sampling clock selection bits (bits 2 and 3) of the Zero cross detection control register (ZCRCON) (Address: 39 16) is set to "00" (when no noise filter is used), the both-sided edge detection function is not available.
Fig. 2.7.1 Structure of Zero cross detection control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selecton reigster (INTEDGE) [Address:3A16]
b
Name
bit INT1/ZCR interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit INT4/A-D conversion interrupt switch bit CNTR0 pin active edge switch bit CNTR1 pin active edge switch bit
Function
0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active 0 : INT4 interrupt 1 : A-D conversion interrupt 0 : Falling edge active 1 : Rising edge active 0 : Falling edge active 1 : Rising edge active
At reset
RW
0 INT0 interrupt edge selection 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 2.7.2 Structure of Interrupt edge selection register
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3819 Group 2.7 Zero cross detection circuit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address:3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T
0 INT0 interrupt request bit
0 0 0
1 INT1/ZCR interrupt request bit 0 : No interrupt request 2
q q
INT2 interrupt request bit Remote control/counter overflow interrupt request bit
3
Serial I/O 1 interrupt request bit q Serial I/O automatic transfer interrupt request bit
q
0 : No interrupt request 1 : Interrupt request
0
T
4 Serial I/O 2 interrupt request
bit Serial I/O 3 interrupt request 5 bit 6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
0 0 0 0
T T T T
T "0" is set by software, but not "1."
Fig. 2.7.3 Structure of Interrupt request register 1
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address:3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1/ZCR interrupt enable bit 2
q q
0 0 0
INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit
3
Serial I/O 1 interrupt enable bit q Serial I/O automatic transfer interrupt enable bit
q
0
4 Serial I/O 2 interrupt enable
bit Serial I/O 3 interrupt enable 5 bit 6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
Fig. 2.7.4 Structure of Interrupt control register 1
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3819 Group 2.7 Zero cross detection circuit
2.7.2 Connection example of Zero cross detection circuit Figure 2.7.5 shows a connection example of the Zero cross detection circuit. R1 is a current limiting resistor. Determine its value according to the current standard of the clamp diode. In this case, the AC input is not the effective value of 100 V but is the peak value of 140 V. R2 is a noise elimination resistor. Connect a resistor of about 1 k near the port.
VCC Effective value Peak value
140 V AC 100 V -140 V
R1
R2
P45/INT1/ZCR
VSS
3819 group
Fig. 2.7.5 Connection example of Zero cross detection circuit
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3819 Group 2.7 Zero cross detection circuit
2.7.3 Zero cross detection circuit application example 1 Clock count using ZCR interrupt (without using a noise filter) Outline : The clock is counted up every second by using the ZCR interrupts. Specifications : * The noise filter is not used. * The commercial frequency (50 Hz or 60 Hz) is input. * The clock is counted up by using the ZCR interrupts. Figure 2. 7. 6 shows a setting of related registers.
Zero cross detection control register (Address:3916) ZCRCON 00 1
Passing through the zero cross detection circuit ( Note) Noise filter sampling clock : without using a noise filter
Interrupt edge selection register (Address:3A16) INTEDGE 0
ZCR active edge : Falling edge active ( Note)
Interrupt request register 1 (Address:3C16) IREQ1 0
Set the INT1/ZCR interrupt request bit to "0"
Interrupt control register 1 (Address:3E16) ICON1 1
INT1/ZCR interrupt : Enabled
Interrupt request register 1 (Address:3C16) IREQ1
ZCR interrupt request Note : When changing the values of bit 0 of the zero cross detection control register and bit 1 of the interrupt edge selection register, make sure the following contents. 1. During changeing, set bit 1 of the interrupt control register 1 to "0". 2. After changeing, set bit 1 of the interrupt request register 1 to "0".
Fig. 2.7.6 Setting of related registers [Clock count using ZCR interrupt (without using a noise filter)]
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3819 Group 2.7 Zero cross detection circuit
Control procedure : Set the related registers according to Figure 2.7.6. At the falling edge of the commercial frequency (50 Hz or 60 Hz), the ZCR interrupt occurs. The clock is counted up every second in the ZCR interrupt processing routine. Figure 2.7.7 shows a control procedure.
RESET Initialization SEI CLT CLD CPUM (Address:3B16), bit6
....
q
All interrupts : Disabled Main clock division ratio : select the high-speed mode Setting of the Zero cross detection control register Set the INT1/ZCR interrupt request bit to "0" ZCR interrupt : Enabled Input 50 Hz (60 Hz) Interrupts : Enabled
0
q
ZCRCON (Address:3916) 000000012 IREQ1 (Address:3C16), bit1 0 NOP ICON1 (Address:3E16), bit1 1 1 second counter 50(60) (Internal RAM) CLI
....
q q
q
q
q
~ ~
ZCR interrupt processing routine CLT (Note 1) CLD (Note 2) Push register to stack Note 1 : When using the index X mode flag (T). Note 2 : When using the decimal mode flag (D).
q
Push into the register used in the interrupt processing routine.
1 second counter - 1
1 second counter = 0? =0 1 second counter 50(60) Clock count up (second-year)
0
q
Input 50 Hz (60 Hz)
Pop registers
q
Pop registers which is pushed to stack .
RTI
Fig. 2.7.7 Control procedure [Clock count using ZCR interrupt (without using a noise filter)]
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3819 Group 2.7 Zero cross detection circuit
2.7.4 Zero cross detection circuit application example 2 Clock count using ZCR interrupt (using a noise filter) Outline : The clock is counted up every second by using the ZCR interrupts. Specifications : * f(XIN)=4 MHz * The noise filter (sampling clock : f(XIN)/256) is used. (Pulse less than 64 s is eliminated as a noise.) * The commercial frequency (50 Hz or 60 Hz) is input. * The clock is counted up by using the ZCR interrupts. Figure 2.7.8 shows a setting of related registers.
Zero cross detection control register (Address:3916) ZCRCON 011 1
Passing through the zero cross detection circuit (Note) Noise filter sampling clock : f(XIN)/256 Selection of one-sided edge detection
Interrupt edge selection register (Address:3A16) INTEDGE 0
ZCR active edge : Falling edge active (Note)
Interrupt request register 1 (Address:3C16) IREQ1 0
Set the INT1/ZCR interrupt request bit to "0"
Interrupt control register 1 (Address:3E16) ICON1 1
INT1/ZCR interrupt : Enabled
Interrupt request register 1 (Address:3C16) IREQ1
ZCR interrupt request Note : When changing the values of bit 0 of the zero cross detection control register and bit 1 of the interrupt edge selection register, make sure the following contents. 1. During changeing, set bit 1 of the interrupt control register 1 (disable ZCR interrupt) to "0". 2. After changeing, set bit 1 of the interrupt request register 1 (no ZCR interrupt request) to "0". However, the value of bit 1 of the interrupt request register 1 is changed with a maximum delay of 2 sampling clocks by using a noise filter. Thus, after changing, set this bit to "0" after a wait of 2 sampling clocks.
Fig. 2.7.8 Setting of related registers [Clock count using ZCR interrupt (using a noise filter)]
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3819 Group 2.7 Zero cross detection circuit
Control procedure : Set the related registers according to Figure 2.7.8. At the falling edge of the commercial frequency (50 Hz or 60 Hz), the ZCR interrupt occurs. The clock is counted up every second in the ZCR interrupt processing routine. Figure 2.7.9 shows a control procedure.
RESET Initialization SEI CLT CLD CPUM (Address:3B16), bit6
q
All interrupts : Disabled Main clock division ratio : select the high-speed mode Setting of the Zero cross detection control register Set the INT1/ZCR interrupt request bit to "0"
0
ZCRCON (Address:3916) 000000012 Wait of 2 sampling clocks IREQ1 (Address:3C16), bit1 0 NOP ICON1 (Address:3E16), bit1 1 1 second counter 50(60) (Internal RAM) CLI
ZCR interrupt processing routine (Note 1)
Fig. 2.7.9 Control procedure [Clock count using ZCR interrupt (using a noise filter)]
....
q
q q
q
q
ZCR interrupt : Enabled Input 50 Hz (60 Hz) Interrupts : Enabled
....
q
~ ~
CLT (Note 2) CLD (Note 3) Push register to stack
q
Note 1 : The ZCR interrupt occurs with delay of the Zero cross by a minimum of 1 sampling clock or a maximum of 2 sampling clocks because a noise filter is used. Note 2 : When using the index X mode flag (T). Note 3 : When using the decimal mode flag (D). Push into the register used in the interrupt processing routine.
1 second counter - 1
1 second counter = 0? =0 1 second counter 50(60) Clock count up (second-year)
0
q
Input 50 Hz (60 Hz)
Pop registers
q
Pop registers which is pushed to stack
RTI
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2.8 Reset
2.8.1 Connection example of reset IC
3819 Group 2.8 Reset
91 1
VCC
Power source
M62022L
GND
3
5
Output
35
RESET
Delay capacity
4
0.1 F
40
VSS
3819 group
Fig. 2.8.1 Example of Poweron reset circuit Figure 2.8.2 shows the system example which switch to the RAM backup mode by detecting a drop of the system power source voltage with the INT interrupt.
System power source voltage +5
91 + 7
VCC
VCC1 RESET
2
5
35
RESET
VCC2
3
INT
6
INT
1
V1 GND Cd
4
3819 group
M62009L, M62009P, M62009FP
Fig. 2.8.2 RAM back-up system
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2.9 Clock generating circuit
2.9.1 Related registers
Timer i
b7 b6 b5 b4 b3 b2 b1 b0 Timer i (Ti) (i = 1, 3) [Address:20 16, 2216]
3819 Group 2.9 Clock generating circuit
B 0 1 2 3 4 5 6 7
q q q
Function
The counter value of the Timer i is set. The value set in this register is written to both the Timer i and the Timer i latch at the same time. When the Timer i is read out, the value (count value) of the Timer i is read out.
At reset
RW
1 1 1 1 1 1 1 1
Fig. 2.9.1 Structure of Timer i (i = 1, 3)
Timer 2
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address:2116]
B 0 1 2 3 4 5 6 7
q q q
Function
The counter value of the Timer 2 is set. The value set in this register is written to both the Timer 2 and the Timer 2 latch at the same time. When the Timer 2 is read out, the value (count value) of the Timer 2 is read out.
At reset
RW
1 0 0 0 0 0 0 0
Fig. 2.9.2 Structure of Timer 2
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3819 Group 2.9 Clock generating circuit
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 12 mode register (T12M) [Address:2816]
B
Name
Function
0 : Operating 1 : Stopped 0 : Operating 1 : Stopped
At reset
RW
0 Timer 1 count stop bit 1 Timer 2 count stop bit 2 Timer 1 count source
0 0 0 0 0 0 0 0
! !
0 : f(XIN)/16 or f(XCIN)/16 1 : f(XCIN) selection bit 3 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0."
4 Timer 2 count source
selection bits
00 : Timer 1 underflow 01 : f(XCIN) 10 : External count input CNTR 0 5 11 : Not available 0 : I/O port 6 Timer 1 output selection bit 1 : Timer 1 output (P46) 7 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0."
b5 b4
Fig. 2.9.3 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address:2916]
B
Name
Function
0 : Operating 1 : Stopped 0 : Operating 1 : Stopped
At reset
RW
0 Timer 3 count stop bit 1 Timer 4 count stop bit 2 Timer 3 count source 3 4 5 6
0 0 0 0 0 0 0 0
! !
0 : f(XIN)/16 or f(XCIN)/16 1 : Timer 2 underflow selection bit Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0." b5 b4 Timer 4 count source 00 : f(XIN)/16 or f(XCIN)/16 selection bits 01 : Timer 3 underflow 10 : External count input CNTR 1 11 : Not available 0 : I/O port Timer 3 output selection bit 1 : Timer 3 output (P47) When this bit is read out, the value is "0."
7 Nothing is allocated for this bit. This is a write disabled bit.
Fig. 2.9.4 Structure of Timer 34 mode register
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3819 Group 2.9 Clock generating circuit
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address:3B16]
B
Name
b1b0
Function
0 0 : Single-chip mode 01: 10: Not available 11: 0 : 0 page 1 : 1 page 0 : Low 1 : High 0 : I/O port function 1 : XCIN-XCOUT oscillating function 0 : Operating 1 : Stopped 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode)
At reset
RW
0 Processor mode bits 1 2 Stack page selection bit 3 XCOUT drivability selection bit 4 Port Xc switch bit 5 Main clock (XIN-XOUT) stop bit 6 Main clock division ratio
0 0 0 1
0
0 1 0
selection bit 7 Internal system clock selection 0 : XIN-XOUT selected bit (middle/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
Fig. 2.9.5 Structure of CPU mode register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address:3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T
0 INT0 interrupt request bit 1 INT1/ZCR interrupt request bit 2
q q
0 0 0
INT2 interrupt request bit Remote control/counter overflow interrupt request bit Serial I/O 1 interrupt request bit Serial I/O automatic transfer interrupt request bit
3
q
0
T
q
4 Serial I/O 2 interrupt request
bit 5 Serial I/O 3 interrupt request bit 6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
0 0 0 0
T T T T
T "0" is set by software, but not "1."
Fig. 2.9.6 Structure of Interrupt request register 1
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3819 Group 2.9 Clock generating circuit
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address:3D16]
b
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T
0 Timer 3 interrupt request bit 1 Timer 4 interrupt request bit 2 Timer 5 interrupt request bit 3 Timer 6 interrupt request bit 4 INT3 interrupt request bit 5
q q
0 0 0 0 0 0
INT4 interrupt request bit A-D conversion interrupt request bit
6
FLD blanking interrupt 0 : No interrupt request request bit 1 : Interrupt request q FLD digit interrupt request bit
q
0
T
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0." T "0" is set by software, but not "1."
0
T
Fig. 2.9.7 Structure of Interrupt request register 2
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address:3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1/ZCR interrupt enable bit 2
q q
0 0 0
INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit
3
Serial I/O 1 interrupt enable bit q Serial I/O automatic transfer interrupt enable bit
q
0
4 Serial I/O 2 interrupt enable
bit Serial I/O 3 interrupt enable 5 bit 6 Timer 1 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
7 Timer 2 interrupt enable bit
Fig. 2.9.8 Structure of Interrupt control register 1
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3819 Group 2.9 Clock generating circuit
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address:3F16]
b
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 Timer 3 interrupt enable bit 1 Timer 4 interrupt enable bit 2 Timer 5 interrupt enable bit 3 Timer 6 interrupt enable bit 4 INT3 interrupt enable bit 5
q q
0 0 0 0 0 0
INT4 interrupt enable bit A-D conversion interrupt enable bit
6
FLD blanking interrupt enable bit q FLD digit interrupt enable bit
q
0
7 Fix this bit to "0."
0
Fig. 2.9.9 Structure of Interrupt control register 2
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2.9.2 Clock generating circuit application examples (1) Status transition upon a power failure Outline : The clock is counted up every second by using the timer interrupt during a power failure. Specifications : * Keep a power consumption as low as possible while maintaining a clock function. * f(XIN) = 4.19 MHz, f(XCIN) = 32.768 kHz * Port processing Input port : Fix to "H" or "L" level in the external unit. Output port : Fix to an output level which does not cause a current flow to the external unit.
3819 Group 2.9 Clock generating circuit
Input port (Note)
Power failure detection signal
3819 group Note : Signal is detected by inputting to each input port, interrupt input pin, and analog input pin.
Fig. 2.9.10 Connection diagram [Status transition upon a power failure]
[Example] When a circuit turns on LED at "L" output level, fix the output level to "H." I/O port : Input port -- Fix to "H" or "L" level in the external unit . Output port -- Output the data which does not consume current. VREF : Supplying to the Reference voltage input pin is stopped by the external circuit. P45/ZCR (using as the input port) : Fix to "H" level in the external unit . Figure 2.9.11 shows a status transition diagram upon a power failure, Figure 2.9.12 shows a setting of related registers, and Figure 2.9.13 shows a control procedure.
Release reset
Detection of power failure
XIN
XCIN
Internal system clock
f(XIN)/8
f(XIN)/2
f(XCIN)/2
Change the internal system clock to f(XIN)/2 (high-speed mode). Selection of XCIN oscillating function
After detecting a power failure, change the internal system clock to f(XCIN) and stop operating of f(XIN).
Fig. 2.9.11 Status transition diagram upon a power failure
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3819 Group 2.9 Clock generating circuit
CPU mode register (Address:3B16) CPUM 0000 00
Main clock f(XIN) : High-speed mode ( Note 1)
CPU mode register (Address:3B16) CPUM 0001
(Note 2) XCIN-XCOUT : Oscillating
00
CPU mode register (Address:3B16) CPUM 1001
(Note 2) Internal system clock : f(XCIN) (low-speed mode)
00
CPU mode register (Address:3B16) CPUM 1011
(Note 2) Main clock f(XIN) : Stopped
00
Note 1 : Only when selecting the high-speed mode. Note 2 : When bit 6 is set to "1", the middle-speed mode is selected.
Fig. 2.9.12 Setting of related registers [Status transition upon a power failure]
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3819 Group 2.9 Clock generating circuit
Control procedure : Set the related registers in the order shown below to prepare for a power failure.
RESET Initialization
q
Middle-speed mode
CPUM (Address:3B 16), bit6 CPUM (Address:3B 16), bit4
0 1
q
q
When select the main clock f(X IN)/2 (high-speed mode) Select the XCIN-XCOUT oscillating function
Detect a power failure? Y CPUM (Address:3B16), bit7 CPUM (Address:3B16), bit5 1(Note) 1(Note)
N
~ ~
q q
Internal system clock : select the low-speed mode f(X CIN). Main clock f(XIN) : Stopped At a power failure, the clock count is performed during processing the timer interrupts (occur every second).
Set so that a timer interrupt occurs every second. Execute the WIT instruction. N
q
Be concluded the condition recovered from a power failure? Y Recovery processing from a power failure
~ ~
Note : Do not switch at the same time.
Fig. 2.9.13 Control procedure [Status transition upon a power failure]
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(2) Counting without clock error during a power failure Outline : It keeps counting without clock errors during a power failure. Specifications : * Keep a power consumption as low as possible while maintaining a clock function. * Keep counting a clock correctly. * f(XIN) = 4.19 MHz, f(XCIN) = 32.768 kHz * The Timer 1 interrupt is used in a normal power state. The Timer 3 interrupt is used during a power failure.
3819 Group 2.9 Clock generating circuit
Input port (Note)
Power failure detection signal
3819 group Note : Signal is detected by inputting to each input port, interrupt input pin, and analog input pin.
* Port processing Input port : Fix to "H" or "L" level in the external Fig. 2.9.14 Connection diagram [Counting without unit. clock errors during a power failure] Output port : Fix to an output level which does not cause a current flow to the external unit. [Example] When a circuit turns on LED at "L" output level, fix the output level to "H". I/O port : Input port -- Fix to "H" or "L" level in the external unit. Output port -- Output the data which does not consume current. VREF : Supplying to the Reference voltage input pin is stopped by the external circuit. P45/ZCR (using as the input port) : Fix to "H" level in the external unit. Figure 2.9.15 shows a timing chart of counting without clock errors during a power failure, Figure 2.9.16 shows a structure of a clock counter, and Figures 2.9.17 and 2.9.18 show a setting of related registers.
Release reset
Detection of power failure
XIN
XCIN
Internal system clock
f(XIN)/8
f(XIN)/2
f(XCIN)/2
Change the internal system clock to f(XIN)/2 (high-speed mode). Selection of XCIN oscillating function
After detecting a power failure, change the internal system clock to f(XCIN) and stop operating of f(XIN).
Fig. 2.9.15 Timing chart of counting without clock errors during a power failure
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3819 Group 2.9 Clock generating circuit
Timer 1 interrupt
Fixed Base counter 1 second counter Timer 1
Timer 3 interrupt
1 minute counter 1 second
f(XIN) = 4.19 MHz
1/16
1/64
244 s
1/256
1/16
1/60
Minute/Hour/Day/ Month/Year
When the system recovers from a power failure, add the switching process time taken for the recovery.

Timer 1
f(XCIN) = 32.768 kHz
1/8
244 s
Timer 2
Timer 3
1/256
1/16
Software timer Hardware timer
Fig. 2.9.16 Structure of a clock counter
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3819 Group 2.9 Clock generating circuit
CPU mode register (Address:3B16) CPUM 0001 00
XCIN-XCOUT : Oscillating
CPU mode register (Address:3B16) CPUM 00 00
Main clock f(XIN) : High-speed mode Internal system clock : f(XIN)/2 (high-speed mode)
Timer 1 (Address:2016) T1 63
Set "division ratio - 1"
Timer 12 mode register (Address:2816) T12M 000 000
Set "0016"
Timer 34 mode register (Address:2916) T34M 0 1 0
Timer 3 count : Operating Timer 3 count source : Timer 2 underflow Timer 3 output selection : I/O port
Interrupt request register 1 (Address:3C16) IREQ1 0
Set the Timer 1 interrupt request bit to "0"
Interrupt request register 2 (Address:3D16) IREQ2 0
Set the Timer 3 interrupt request bit to "0"
Fig. 2.9.17 Setting of related registers (1) [Counting without clock errors during a power failure]
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3819 Group 2.9 Clock generating circuit
Interrupt control register 1 (Address:3E16) ICON1 1
Timer 1 interrupt : Enabled
CPU mode register (Address:3B16) CPUM 1001 00
Internal system clock : f(XCIN) (low-speed mode)
CPU mode register (Address:3B16) CPUM 101 00
Main clock f(XIN) : Stopped
Interrupt control register 1 (Address:3E16) ICON1 0
Timer 1 interrupt : Disabled
Interrupt control register 2 (Address:3F16) ICON2 0 1
Timer 3 interrupt : Enabled
Timer 1 (Address:2016) T1 7 Timer 2 (Address:2116) T2 255 Timer 3 (Address:2216) T3 15
Set "division ratio - 1" to each timer
Fig. 2.9.18 Setting of related registers (2) [Counting without clock errors during a power failure]
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3819 Group 2.9 Clock generating circuit
Control procedure : Set the related registers in the order shown below to prepare for a power failure.
RESET Initialization
q
Middle-speed mode
CPUM (Address:3B 16), bit4
1
q
Select the XCIN-XCOUT oscillating function Main clock division ratio : select the high-speed mode Set for being count the base and 1 second counters during the Timer 1 interrupts. In the normal power state, these software counters generate one second.
CPUM (Address:3B16), bit6 (Address:2016) T1 T12M (Address:2816) T34M (Address:2916), bit6, bit0 T34M (Address:2916), bit2 IREQ1 (Address:3C16), bit6 IREQ2 (Address:3D16), bit0 (Internal RAM) Base counter 1second counter (Internal RAM) ICON1 (Address:3E16), bit6
0 64-1 0016 0 1 0 0 256-1 16-1 1
q
q
Detect a power failure? Y T12M (Address:2816), bit2 ICON1 (Address:3E16), bit6 CPUM (Address:3B16), bit7 CPUM (Address:3B16), bit5 IREQ1 (Address:3C16), bit6 IREQ2 (Address:3D16), bit0 (Address:2016) T1 (Address:2116) T2 (Address:2216) T3 ICON2(Address:3F16), bit0
N
~ ~
1 0 1(Note) 1(Note) 0 0 8-1 256-1 16-1 1
q q q q q
q
Timer 1 count source : f(X CIN) Timer 1 interrupt : Disabled Internal system clock : select the low-speed mode f(X CIN). Main clock f(XIN) : Stopped Set for generating the Timer 3 interrupts every second. Generate 1 second by the hardware timer during a power failure. Timer 3 interrupt : Enabled Generate the Timer 3 interrupts every second (recover from a wait mode)
q
q
Execute the WIT instruction
N
Be concluded the condition recovered from a power failure? Y Recovery processing from a power failure Note : Do not switch at the same time.
~ ~
Fig. 2.9.19 Control procedure (1) [Counting without clock errors during a power failure]
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3819 Group 2.9 Clock generating circuit
Timer 3 interrupt processing routine
Push register to stack etc.
Fig. 2.9.20 Control procedure (2) [Counting without clock errors during a power failure]
....
Count 1 minitue counter (Internal RAM) 1 minitue counter overflow ? Y Renew Time, Day, Month, Year N
~ ~
RTI
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3.1 Notes on use 3.2 Countermeasures against noise 3.3 Control registers 3.4 Mask ROM ordering method 3.5 Mark specification form 3.6 Package outline 3.7 Memory map 3.8 Pin configuration
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3. APPENDIX
3.1 Notes on use
3.1.1 Notes on Interrupts For the products able to switch the external interrupt detection edge, switch it as the following sequence. Reason The interrupt circuit recognizes the switching of the detection edge as the change of external input signals. This may cause an unnecessary interrupt.
3819 Group 3.1 Notes on use
Clear an interrupt enable bit to "0" (interrupt disabled) Switch the detection edge Clear an interrupt request bit to "0" (no interrupt request issued) NOP (one or more instructions) Set the interrupt enable bit to "1" ( interrupt enabled )
Fix the bit 7 of the interrupt control register 2 to "0". Figure 3.1.1 shows the structure of the interrupt control register 2.
b7
b0 Interrupt control register 2 Address 003F16
0
Interrupt control bits Not used Fix this bit to "0"
Fig. 3.1.1 Structure of interrupt control register 2 3.1.2 Notes on the FLD controller and the serial I/O automatic transfer function When using the FLD controller function and the serial I/O automatic transfer function, set the system clock to the highspeed mode or the middle-speed mode.
3.1.3 Notes on the A-D converter Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 F to 1 F. Further, be sure to verify the operation of application products on the user side. Reason An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. This may cause the A-D comparison precision to be worse. Pins AVCC and AVSS are A-D converter power source pins. Connect them as following : qAVCC : Connect to the VCC line which is the analog system qAVSS : Connect to the VSS line which is the analog system
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3819 Group 3.1 Notes on use
The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Thus, make sure the following during an A-D conversion. q f(XIN) is 500 kHz or more . q Do not execute the STP instruction and WIT instruction.
3.1.4 Notes on the RESET pin n case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the VSS pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : qMake the length of the wiring which is connected to a capacitor. qBe sure to check the operation of application products on the user side. Reason If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may cause a microcomputer failure.
3.1.5 Notes on input and output pins In stand-by state* for low-power dissipation, do not make input levels of an input and an I/O port "undefined," especially for the I/O ports of the P-channel and the N-channel open-drain. Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a resistor. When determining a resistance value, note the following points: qExternal circuit qVariation of output levels during the ordinary operation When using built-in pull-up or pull-down resistor as an option, note on varied current values. qWhen setting as an input port : Fix its input level qWhen setting as an output port : Prevent current from flowing out to external Reason Even when setting as an output port with its direction register, in the following state : qP-channel......when the content of the data register (port latch) is "0" qN-channel......when the content of the data register (port latch) is "1" the transistor becomes the OFF state, which causes the ports to be the high-impedance state. Note that the level becomes "undefined" depending on external circuits. Accordingly, the potential which is input to the input buffer in a microcomputer is unstable in the state that input levels of an input and an I/O port are "undefined." This may cause power source current. * stand-by state : the stop mode by executing the STP instruction
the wait mode by executing the WIT instruction
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3819 Group 3.1 Notes on use
When the data register (port latch) of an I/O port is modified with the bit managing instruction*, the value of the unspecified bit may be changed. Reason The bit managing instructions are read-modify-write form instructions for reading and writing data by a byte unit. Accordingly, when these instructions are executed on a bit of the data register of an I/O port, the following is executed to all bits of the data register. qAs for a bit which is set to an input port : The pin state is read in the CPU, and is written to this bit after bit managing. qAs for a bit which is set to an output port : The bit value is read in the CPU, and is written to this bit after bit managing. Note the following : qEven when a port which is set as an output port is changed for an input port, its data register holds the output data. qAs for a bit of which is set to an input port , its value may be changed even when not specified with a bit managing instruction in case where the pin state differs from its data register contents * bit managing instructions : SEB and CLB instruction When not using the A-D converter, connect the A-D converter power source AVSS pin as follows : qAVSS : Connect to the VSS pin Reason If the AVSS pin is opened, the microcomputer may have a failure because of noise or others. 3.1.6 Notes on clock synchronous serial I/O When an external clock is used as the synchronous clock for data transmission, set the transmit enable bit to "1" at "H" of the SCLK input level. Also, write data to the transmit buffer register at "H" of the SCLK input level.
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3. APPENDIX
3.1.7 Notes on built-in PROM
3819 Group 3.1 Notes on use
(1) Programming adapter To write into or read from data the internal PROM, use the dedicated programming adapter and general-purpose PROM programmer as shown in Table 3.1.1. Table 3.1.1 Programming adapter Microcomputer M38197EAFS M38197EAFP (one-time blank) PCA4738F-100A Programming adapter PCA4738L-100A
(2) Write and read In PROM mode, operation is the same as that of the M5M27C101, but programming conditions of PROM programmer are not set automatically because there are no built-in device ID codes. Accurately set the following conditions for data write/read. Do not apply 21 V to the Vpp pin (is also used as port P40), or the product may be permanently damaged. q Programming voltage : 12.5 V q Setting of programming adapter switch : refer to "Table 3.1.2" q Setting of PROM programmer address : refer to "Table 3.1.3" Table 3.1.2 Setting of programming adapter switch Programming adapter PCA4738L-100A PCA4738F-100A Table 3.1.3 Setting of PROM programmer address Microcomputer M38197EAFS M38197EAFP Address : 608016 Address : FFFD16 PROM programmer start address (Note) PROM programmer completion address (Note) P-channel SW 1 SW 2 OFF (CMOS) OFF SW 3
Note : Because addresses 600016 to 607F16 and FFFE16 to FFFF16 are the reserved ROM area, do not use these addresses. (3) Erasing Contents of the windowed EPROM (38197 EAFS) are erased by an ultraviolet light source with the wavelength 2537-Angstrom . At least 15 W*sec/cm 2 are required to erase EPROM contents.
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3. APPENDIX
3819 Group 3.2 Countermeasures against noise
3.2 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.2.1 Shortest wiring length The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for the RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Reason The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
RESET VSS
Reset circuit VSS
RESET VSS
Fig. 3.2.1 Wiring for the RESET pin (2) Wiring for clock input/output pins qMake the length of wiring which is connected to clock I/O pins as short as possible. qMake the length of wiring (within 20mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. qSeparate the VSS pattern only for oscillation from other VSS patterns. Reason A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
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3819 Group 3.2 Countermeasures against noise
Noise
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
XIN XOUT VSS
XIN XOUT VSS
XIN XOUT VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 3.2.2 Wiring for clock I/O pins (3) Wiring for the VPP pin of the One Time PROM version and the eprom version qMake the length of wiring which is connected to the VPP pin as short as possible. qConnect an approximately 5 k resistor to the VPP pin in serial. Reason The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for wiring flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal in struction codes or data are read from the built-in PROM, which may cause a program runaway.
3819 group Approximately 5k P40/VPP
Fig. 3.2.3 Wiring for the VPP pin of the One Time PROM and the EPROM version
3.2.2 Connection of a bypass capacitor across the Vss line and the Vcc line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: qConnect a bypass capacitor across the VSS pin and the VCC pin at equal length . qConnect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. qUse lines with a larger diameter than other signal lines for VSS line and VCC line.
VCC
VSS
Fig. 3.2.4 Bypass capacitor across the VSS line and the VCC line
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3. APPENDIX
3819 Group 3.2 Countermeasures against noise
3.2.3 Wiring to analog input pins qConnect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. qConnect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Reason Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from the VSS pin, noise on the GND line may enter a microcomputer through the capacitor. 3.2.4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping an oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping an oscillator away from signal lines where potential levels change frequently Install an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Reason Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
Noise Sensor Microcomputer Analog input pin
VSS
Fig.3.2.5 Analog signal line and a resistor and a capacitor
Microcomputer Mutual inductance M Large current GND
Fig.3.2.6 Wiring for a large current signal line
XIN XOUT VSS
Do not cross
CNTR XIN XOUT VSS
Fig.3.2.7 Wiring to a signal line where potential levels change frequently
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3819 Group 3.2 Countermeasures against noise
3.2.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: qConnect a resistor of 100 or more to an I/O port in series. qAs for an input port, read data several times by a program for checking whether input levels are equal or not. qAs for an output port, since the output data may reverse because of noise, rewrite data to its data register at fixed periods. qRewirte data to direction registers and pull-up control registers (only the product having it) at fixed periods.
Data bus
Direction register Data register I/O port pins
Noise
Noise
Fig. 3.2.8 Setup for I/O ports
When a direction register is set to input port again at fixed periods, a several-nanosecond short pulse may be output from this port. If this is undesirable, connect a capacitor to this port to remove the noise pulse. 3.2.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
Main routine (SWDT) N CLI Main processing
Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine
N
(SWDT) = N? =N
Interrupt processing
routine errors errors qAssigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. Fig. 3.2.9 Watchdog timer by software The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. qWatches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. qDetects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: x If the SWDT contents do not change after interrupt processing If the changed SWDT contents are abnormal (In Figure 3.2.9, the main routine determines that the interrupt processing routine has failed only if the SWDT contents do not change).
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3819 Group 3.2 Countermeasures against noise
qDecrements the SWDT contents by 1 at each interrupt processing. qDetermins that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). qDetects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: x If the SWDT contents are not initialized to the initial value N but continued to decrement and if they exceed the limit (and reach 0 or less).
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3. APPENDIX
3.3 Control registers
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
3819 Group 3.3 Control registers
Port Pi direction register (PiD) (i = 4, 5, 6, 7, 8, A, B) [Address:09 16, 0B16, 0D16, 0F16, 1116, 1516, 1716]
B
Name
Function
0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode (Note)
At reset
RW
! ! ! ! ! ! ! !
0 Port Pi direction register 1 2 3 4 5 6 7
0 0 0 0 0
(Note)
0 0 0
Note : Port P4 direction register [Address:09 16] Ports P40 and P45 are input ports. Accordingly, these bits do not have a direction register function.
Fig. 3.3.1 Structure of Port Pi direction register (i = 4, 5, 6, 7, 8, A, B)
Port P2 direction register
b7 b6 b5 b4 b3 b2 b1 b0 Port P2 direction register (P2D) [Address:0516]
Name Function B 0 Because P20 to P23 are output ports, these bits do not have a 1 direction register function and nothing is allocated. 2 3 0 : Port P24 input mode 4 Port P2 direction register 5 6 7
1 : Port P24 output mode 0 : Port P25 input mode 1 : Port P25 output mode 0 : Port P26 input mode 1 : Port P26 output mode 0 : Port P27 input mode 1 : Port P27 output mode
At reset
RW
! ! ! ! ! ! ! ! ! ! ! !
1 1 1 1 0 0 0 0
Fig. 3.3.2 Structure of Port P2 direction register
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3819 Group 3.3 Control registers
Serial I/O automatic transfer data pointer
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O automatic transfer data pointer (SIODP) [Address:1816]
B
Function
At reset
RW
0 Indicate an address of Serial I/O automatic transfer RAM. 1 2 3 4 5 Nothing is allocated for these bits. These are write disabled bits. 6 When these bits are read out, the values are "0." 7
? ? ? ? ? 0 0 0
! ! !
Fig. 3.3.3 Structure of Serial I/O automatic transfer data pointer
Serial I/O 1 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O 1 control register (SIO1CON) [Address:1916]
B
Name
b2 b1b0
Function
000 : f(XIN)/8 or f(XCIN)/8 001 : f(XIN)/16 or f(XCIN)/16 010 : f(XIN)/32 or f(XCIN)/32 011 : f(XIN)/64 or f(XCIN)/64 110 : f(XIN)/128 or f(XCIN)/128 111 : f(XIN)/256 or f(XCIN)/256 0 : I/O port T 1 : SOUT1, SCLK11, SCLK12 signal pins 0 : I/O port T ( Note) 1 : SRDY1/CS signal pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
At reset
RW
0 Internal synchronous clock
selection bits
0 0 0 0 0 0 0 0
1 2 3 Serial I/O 1 port selection bit 4 5 6 7
(P65,P66,P67T ) SRDY1 output selection bit (P67) Transfer direction selection bit Synchronous clock selection bit P65/SOUT1 P-channel output disable bit
T
Valid only in the Serial I/O automatic transfer mode
Note : When an external clock is selected in the serial I/O 1 automatic transfer mode, the SRDY1 signal pin is used as the CS signal input pin.
Fig. 3.3.4 Structure of Serial I/O 1 control register
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3819 Group 3.3 Control registers
Serial I/O automatic transfer control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O automatic transfer control register (SIOAC) [Address:1A16]
B
Name
Function
0 : Serial I/O ordinary mode (serial I/O 1 interrupt) 1 : Automatic transfer mode (serial I/O automatic transfer interrupt) 0 : Transfer completion 1 : Transferring (starts by writing "1") 0 : Fullduplex (transmit / receive) mode 1 : Transmit-only mode
At reset
RW
0 Automatic transfer control bit
0
1 Automatic transfer start bit
0 0
2 Transfer mode switch bit 3 Synchronous clock output
pin selection bit
0 : SCLK11 1 : SCLK12 4 Nothing is allocated for these bits. These are write disabled bits. 5 When these bits are read out, the values are "0."
0 0 0 0 0
! ! ! !
6 7
Fig. 3.3.5 Structure of Serial I/O automatic transfer control register
Serial I/O automatic transfer interval register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O automatic transfer interval register (SIOAI) [Address:1C16]
B 0 Ti = (n + 2) ! Tc 1 2 3 4
Function
Ti = a length of transfer interval n = a setting value Tc = a length of a bit of transfer clock
At reset
RW
0 0 0 0 0 0 0 0
! ! !
5 Nothing is allocated for these bits. These are write disabled bits. 6 When these bits are read out, the values are "0." 7
Fig. 3.3.6 Structure of Serial I/O automatic transfer interval register
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3819 Group 3.3 Control registers
Serial I/O 2 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O 2 control register (SIO2CON) [Address:1D16]
B
Name
b2 b1b0
Function
000 : f(XIN)/8 or f(XCIN)/8 001 : f(XIN)/16 or f(XCIN)/16 010 : f(XIN)/32 or f(XCIN)/32 011 : f(XIN)/64 or f(XCIN)/64 110 : f(XIN)/128 or f(XCIN)/128 111 : f(XIN)/256 or f(XCIN)/256 0 : I/O port 1 : SOUT2, SCLK2 signal pins 0 : I/O port 1 : SRDY2 signal pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
At reset
RW
0 Internal synchronous clock
selection bits
0 0 0 0 0 0 0
0
1 2 3 Serial I/O 2 port selection bit
(P51,P52 ) 4 SRDY2 output selection bit (P53) Transfer direction selection bit 5
6 Synchronous clock selection
bit
7 P51/SOUT2 P-channel output
disable bit
Fig. 3.3.7 Structure of Serial I/O 2 control register
Serial I/O 3 control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O 3 control register (SIO3CON) [Address:1E16]
B
Name
b2 b1b0
Function
000 : f(XIN)/8 or f(XCIN)/8 001 : f(XIN)/16 or f(XCIN)/16 010 : f(XIN)/32 or f(XCIN)/32 011 : f(XIN)/64 or f(XCIN)/64 110 : f(XIN)/128 or f(XCIN)/128 111 : f(XIN)/256 or f(XCIN)/256 0 : I/O port 1 : SOUT3, SCLK3 signal pins 0 : I/O port 1 : SRDY3 signal pin 0 : LSB first 1 : MSB first 0 : External clock 1 : Internal clock 0 : CMOS output (in output mode) 1 : N-channel open-drain output (in output mode)
At reset
RW
0 Internal synchronous clock
selection bits
0 0 0 0 0 0 0 0
1 2 3 Serial I/O 3 port selection bit 4 5 6 7
(P55,P56 ) SRDY3 output selection bit (P57) Transfer direction selection bit Synchronous clock selection bit P55/SOUT3 P-channel output disable bit
Fig. 3.3.8 Structure of Serial I/O 3 control register
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3819 Group 3.3 Control registers
Timer 12 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 12 mode register (T12M) [Address:28 16]
B
Name
Function
At reset
RW
0 : Operating 1 : Stopped 0 : Operating 1 Timer 2 count stop bit 1 : Stopped 0 : f(XIN)/16 or f(XCIN)/16 Timer 1 count source 2 1 : f(XCIN) selection bit 3 Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0. "
0 Timer 1 count stop bit
0 0 0 0 0 0 0 0
! !
4 Timer 2 count source
selection bits
00 : Timer 1 underflow 01 : f(XCIN) 10 : External count input CNTR 0 5 11 : Not available 0 : I/O port 6 Timer 1 output selection bit 1 : Timer 1 output (P46) Nothing is allocated for this bit. It is a write disabled bit. 7 When this bit is read out, the value is "0. "
b5 b4
Fig. 3.3.9 Structure of Timer 12 mode register
Timer 34 mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address:2916]
B
Name
Function
At reset
RW
0 Timer 3 count stop bit 1 2 3 4 5 6 7
0 : Operating 1 : Stopped 0 : Operating Timer 4 count stop bit 1 : Stopped 0 : f(XIN)/16 or f(XCIN)/16 Timer 3 count source 1 : Timer 2 underflow selection bit Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0. " b5 b4 Timer 4 count source 00 : f(XIN)/16 or f(XCIN)/16 selection bits 01 : Timer 3 underflow 10 : External count input CNTR 1 11 : Not available 0 : I/O port Timer 3 output selection bit 1 : Timer 3 output (P47) Nothing is allocated for this bit. It is a write disabled bit. When this bit is read out, the value is "0. "
0 0 0 0 0 0 0 0
! !
Fig. 3.3.10 Structure of Timer 34 mode register
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3819 Group 3.3 Control registers
Timer 56 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Timer 56 mode register (T56M) [Address:2A16]
B
Name
Function
0 : Operating 1 : Stopped 0 : Operating 1 : Stopped 0 : f(XIN)/16 or f(XCIN)/16 1 : Timer 4 underflow 0 : Timer mode 1 : PWM mode
b5 b4
At reset
RW
0 Timer 5 count stop bit 1 Timer 6 count stop bit 2 Timer 5 count source
selection bit 3 Timer 6 operation mode selection bit 4 Timer 6 count source selection bits
0 0 0 0 0 0 0 0
5 6 Timer 6 (PWM)
output selection bit (P6 1)
00 : f(XIN)/16 or f(XCIN)/16 01 : Timer 5 underflow 10 : Timer 4 underflow 11 : Not available 0 : I/O port 1 : Timer 6 output
7 Fix this bit to "0."
Fig. 3.3.11 Structure of Timer 56 mode register
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3819 Group 3.3 Control registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0 AD/DA control register (ADCON) [Address:2C16]
B
Name
b3 b2 b1 b0
Function
0 0 0 0 : P70/AN0 0 0 0 1 : P71/AN1 0 0 1 0 : P72/AN2 0 0 1 1 : P73/AN3 0 1 0 0 : P74/AN4 0 1 0 1 : P75/AN5 0 1 1 0 : P76/AN6 0 1 1 1 : P77/AN7 1 0 0 0 : P50/SIN2/AN8 1 0 0 1 : P51/SOUT2/AN9 1 0 1 0 : P52/SCLK2/AN10 1 0 1 1 : P53/SRDY2/AN11 1 1 0 0 : P54/SIN3/AN12 1 1 0 1 : P55/SOUT3/AN13 1 1 1 0 : P56/SCLK3/AN14 1 1 1 1 : P57/SRDY3/AN15
At reset
RW
0 Analog input pin selection bits
0
1
0
2
0
3
0
4 A-D conversion completion bit 0 : Conversion in progress
1 : Conversion completed 5 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0." 0 : Disable 6 D-A output enable bit 1 : Enable
1 0 0 0
! !
7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0."
Fig. 3.3.12 Structure of AD/DA control register
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3819 Group 3.3 Control registers
Interrupt interval determination register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt interval determination register (IID) [Address:3016]
B 0 1 2 3 4 5 6 7
Function
This register stores the values obtaind by counting the following interval with a counter sampling clock. Falling edge interval Rising edge interval Both-sided edge interval (selected by the interrupt edge selection register) This register is read-only.
q q q
At reset
RW
! ! ! ! ! ! ! !
? ? ? ? ? ? ? ?
Note : When the noise filter sampling clock selection bits (bits 2 and 3) of the Interrupt interval determination control register (IIDCON) (Address: 31 16) is set to "00" (when no noise filter is used), the both-sided edge detection function is not available.
Fig. 3.3.13 Structure of Interrupt interval determination register
Interrupt interval determination control register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt interval determination control register (IIDCON) [Address:3116]
B
Name
circuit operating selection bit
Function
1 : Operating 0 : f(XIN)/256 1 : f(XIN)/512 00 : Filter stop 01 : f(XIN)/64 10 : f(XIN)/128 11 : f(XIN)/256
At reset
RW
0 Interrupt interval determination 0 : Stopped 1 Counter sampling clock
selection bit 2 Noise filter sampling clock selection bits (INT 2)
0 0 0 0 0 0 0 0
! ! !
3 4 One-sided/both-sided edge
0 : One-sided edge detection 1 : Both-sided edge detection (Note) detection selection bit 5 Nothing is allocated for these bits. These are write disabled bits. 6 When these bits are read out, the values are "0."
7
Note : When the noise filter sampling clock selection bits (bits 2 and 3) of the Interrupt interval determination control register (IIDCON) (Address: 31 16) is set to "00" (when no noise filter is used), the both-sided edge detection function is not available.
Fig. 3.3.14 Structure of Interrupt interval determination control register
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3819 Group 3.3 Control registers
Port P0 segment/digit switch register
b7 b6 b5 b4 b3 b2 b1 b0 Port P0 segment/digit switch register (P0SDR) [Address:3216]
Name B 0 Port P0 segment/digit
switch register
Function
0 : DIG0 1 : SEG32 0 : DIG1 1 : SEG33 0 : DIG2 1 : SEG34 0 : DIG3 1 : SEG35 0 : DIG4 1 : SEG36 0 : DIG5 1 : SEG37 0 : DIG6 1 : SEG38 0 : DIG7 1 : SEG39
At reset
RW
0 0 0 0 0 0 0 0
1 2 3 4 5 6 7
Fig. 3.3.15 Structure of Port P0 segment/digit switch register
Port P2 digit/port switch register
b7 b6 b5 b4 b3 b2 b1 b0 Port P2 digit/port switch register (P2DPR) [Address:33 16]
B
register
Name
Function
At reset
RW
0 Port P2 digit/port switch 1 2 3 4 5 6 7
0 : Port P20 output-only 1 : DIG16 0 : Port P21 output-only 1 : DIG17 0 : Port P22 output-only 1 : DIG18 0 : Port P23 output-only 1 : DIG19 Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0."
0 0 0 0 0 0 0 0
! ! ! !
Fig. 3.3.16 Structure of Port P2 digit/port switch register
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3819 Group 3.3 Control registers
Port P8 segment/port switch register
b7 b6 b5 b4 b3 b2 b1 b0 Port P8 segment/port switch register (P8SPR) [Address:34 16]
B Name 0 Port P8 segment/port
switch register
Function
0 : Port P80 for I/O 1 : SEG8 0 : Port P81 for I/O 1 : SEG9 0 : Port P82 for I/O 1 : SEG10 0 : Port P83 for I/O 1 : SEG11 0 : Port P84 for I/O 1 : SEG12 0 : Port P85 for I/O 1 : SEG13 0 : Port P86 for I/O 1 : SEG14 0 : Port P87 for I/O 1 : SEG15
At reset
RW
0 0 0 0 0 0 0 0
1 2 3 4 5 6 7
Fig. 3.3.17 Structure of Port P8 segment/port switch register
Port PA segment/port switch register
b7 b6 b5 b4 b3 b2 b1 b0 Port PA segment/port switch register (PASPR) [Address:3516]
B
Name
switch register
Function
0 : Port PA0 for I/O 1 : SEG0 0 : Port PA1 for I/O 1 : SEG1 0 : Port PA2 for I/O 1 : SEG2 0 : Port PA3 for I/O 1 : SEG3 0 : Port PA4 for I/O 1 : SEG4 0 : Port PA5 for I/O 1 : SEG5 0 : Port PA6 for I/O 1 : SEG6 0 : Port PA7 for I/O 1 : SEG7
At reset
RW
0 Port PA segment/port 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Fig. 3.3.18 Structure of Port PA segment/port switch register
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3819 Group 3.3 Control registers
FLDC mode register 1
b7 b6 b5 b4 b3 b2 b1 b0 FLDC mode register 1 (FLDM1) [Address:3616]
B
Name
b1b0
Function
0 0 : FLD digit interrupt (at rising edge of each digit) 0 1 : 1 ! Tdisp 1 0 : 2 ! Tdisp FLD blanking 1 1 : 3 ! Tdisp interrupt (at falling edge of the last digit)
b5 b4 b3 b2
At reset
RW
0 Tscan control bits
0
1
0 0
2 Toff control bit
3
4
5
6 7
0 0 0 0 : 1/16 ! Tdisp 0 0 0 1 : 2/16 ! Tdisp 0 0 1 0 : 3/16 ! Tdisp 0 0 1 1 : 4/16 ! Tdisp 0 1 0 0 : 5/16 ! Tdisp 0 1 0 1 : 6/16 ! Tdisp 0 1 1 0 : 7/16 ! Tdisp 0 1 1 1 : 8/16 ! Tdisp 1 0 0 0 : 9/16 ! Tdisp 1 0 0 1 : 10/16 ! Tdisp 1 0 1 0 : 11/16 ! Tdisp 1 0 1 1 : 12/16 ! Tdisp 1 1 0 0 : 13/16 ! Tdisp 1 1 0 1 : 14/16 ! Tdisp 1 1 1 0 : 15/16 ! Tdisp 1 1 1 1 : 16/16 ! Tdisp Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0." High-breakdown-voltage 0 : Strong drivability drivability selection bit 1 : Weak drivability (Setting of digit/segment OFF time)
0
0
0
0 0
!
Fig. 3.3.19 Structure of FLDC mode register 1
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3. APPENDIX
3819 Group 3.3 Control registers
FLDC mode register 2
b7 b6 b5 b4 b3 b2 b1 b0 FLDC mode register 2 (FLDM2) [Address:3716]
B
Name
Function
At reset
RW
0 : Ordinary mode (P0,P1,P20-P23,P3,P8,P9,PA) 1 : Automatic display mode 0 : Display stopped 1 Display start bit 1 : Display in progress (display starts by writing "1" to this bit which is set to "0".)
0 Automatic display control bit
0 0
2
3
Tdisp control bits (digit time setting) (at 8 MHz oscillation frequency)
b5 b4 b3 b2
4
5
0 0 0 0 : 128 s 0 0 0 1 : 256 s 0 0 1 0 : 384 s 0 0 1 1 : 512 s 0 1 0 0 : 640 s 0 1 0 1 : 768 s 0 1 1 0 : 896 s 0 1 1 1 : 1024 s 1 0 0 0 : 1152 s 1 0 0 1 : 1280 s 1010 Not available 1111
0
0
0
0
6 P10 segment/digit switch bit 7 P11 segment/digit switch bit
0 : Digit (DIG8) 1 : Segment (SEG 40) 0 : Digit (DIG9) 1 : Segment (SEG 41)
....
0 0
Fig. 3.3.20 Structure of FLDC mode register 2
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3819 Group 3.3 Control registers
FLD data pointer
b7 b6 b5 b4 b3 b2 b1 b0 FLD data pointer (FLDDP) [Address:38 16]
B
Function
the FLD automatic display RAM.
At reset
RW
! ! ! ! ! ! ! !
0 Indicate the address of data which is transfered to the segment of 1 2 3 4 5 6 7 Nothing is allocated for this bit. This is a write disabled bit.
When this bit is read out, the value is "0."
? ? ? ? ? ? ? 0
Fig. 3.3.21 Structure of FLD data pointer
FLD data pointer reload register
b7 b6 b5 b4 b3 b2 b1 b0 FLD data pointer reload register (FLDDP) [Address:3816]
B
Function
At reset
RW
! ! ! ! ! ! ! !!
0 Indicate the first digit address of the high-order segment. 1 2 3 4 5 6 7 Nothing is allocated for this bit. This is a write disabled bit.
? ? ? ? ? ? ? ?
Fig. 3.3.22 Structure of FLD data pointer reload register
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3. APPENDIX
3819 Group 3.3 Control registers
Zero cross detection control register
b7 b6 b5 b4 b3 b2 b1 b0 Zero cross detection control register (ZCRCON) [Address:3916]
B
Name
selection bit
Function
0 : Without passing through zero cross detection comparator 1 : Passing through zero cross detection comparator
At reset
RW
0 Zero cross detection ON/OFF
0
1 Nothing is allocated for this bit. It is a write disabled bit.
When this bit is read out, the value is "0."
b3 b2
0 0 0 0 0 0
!
2 Noise filter sampling
clock selection bits 3 (INT1)
4 5 6 7
00 : Note use noise filter 01 : f(XIN)/64 or f(XCIN)/64 10 : f(XIN)/128 or f(XCIN)/128 11 : f(XIN)/256 or f(XCIN)/256 0 : One-sided edge detection One-sided/both-sided edge 1 : Both-sided edges detection ( Note) detection selection bit Nothing is allocated for these bits. These are write disabled bits. When these bits are read out, the values are "0." Zero cross detection circuit 0 : Less than 0 V input bit (read-only) 1 : 0 V or more
! ! !
Note : When the noise filter sampling clock selection bits (bits 2 and 3) of the Zero cross detection control register (ZCRCON) (Address: 39 16) is set to "00" (when no noise filter is used), the both-sided edge detection function is not available.
Fig. 3.3.23 Structure of Zero cross detection control register
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt edge selecton reigster (INTEDGE) [Address:3A16]
b 0 1 2 3 4 5 6 7
Name
Function
At reset
RW
0 : Falling edge active INT0 interrupt edge selection 1 : Rising edge active bit 0 : Falling edge active INT1/ZCR interrupt edge 1 : Rising edge active selection bit 0 : Falling edge active INT2 interrupt edge selection 1 : Rising edge active bit 0 : Falling edge active INT3 interrupt edge selection 1 : Rising edge active bit 0 : Falling edge active INT4 interrupt edge selection 1 : Rising edge active bit INT4/A-D conversion interrupt 0 : INT4 interrupt 1 : A-D conversion interrupt switch bit CNTR0 pin active edge switch 0 : Falling edge active 1 : Rising edge active bit CNTR1 pin active edge switch 0 : Falling edge active 1 : Rising edge active bit
0 0 0 0 0 0 0 0
Fig. 3.3.24 Structure of Interrupt edge selection register
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CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0 CPU mode register (CPUM) [Address:3B16]
3819 Group 3.3 Control registers
B
Name
b1b0
Function
0 0 : Single-chip mode 01: 10: Not available 11: 0 : 0 page 1 : 1 page 0 : Low 1 : High 0 : I/O port function 1 : XCIN-XCOUT oscillating function 0 : Operating 1 : Stopped
At reset
RW
0 Processor mode bits 1 2 Stack page selection bit 3 XCOUT drivability selection bit 4 Port Xc switch bit 5 Main clock (XIN-XOUT) stop bit 6 Main clock division ratio
0 0 0 1 0 0 1 0
0 : f(XIN)/2 (high-speed mode) selection bit 1 : f(XIN)/8 (middle-speed mode) 7 Internal system clock selection 0 : XIN-XOUT selected bit (middle/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)
Fig. 3.3.25 Structure of CPU mode register
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 1 (IREQ1) [Address:3C16]
B
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T
0 INT0 interrupt request bit 1 INT1/ZCR interrupt request bit 2
q q
0 0 0
3
q
q
INT2 interrupt request bit Remote control/counter overflow interrupt request bit Serial I/O 1 interrupt request bit Serial I/O automatic transfer interrupt request bit
0
T
4 Serial I/O 2 interrupt request
bit 5 Serial I/O 3 interrupt request bit 6 Timer 1 interrupt request bit
7 Timer 2 interrupt request bit
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
0 0 0 0
T T T T
T "0" is set by software, but not "1."
Fig. 3.3.26 Structure of Interrupt request register 1
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3819 Group 3.3 Control registers
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request reigster 2 (IREQ2) [Address:3D16]
b
Name
Function
0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset
RW
T T T T T T
0 Timer 3 interrupt request bit 1 Timer 4 interrupt request bit 2 Timer 5 interrupt request bit 3 Timer 6 interrupt request bit 4 INT3 interrupt request bit 5
q q
0 0 0 0 0 0
INT4 interrupt request bit A-D conversion interrupt request bit
0 : No interrupt request FLD blanking interrupt 1 : Interrupt request request bit q FLD digit interrupt request bit 7 Nothing is allocated for this bit. This is a write disabled bit. When this bit is read out, the value is "0."
6
q
0
T
0
T
T "0" is set by software, but not "1."
Fig. 3.3.27 Structure of Interrupt request register 2
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address:3E16]
B
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 INT0 interrupt enable bit 1 INT1/ZCR interrupt enable bit 2
q q
0 0 0
INT2 interrupt enable bit Remote control/counter overflow interrupt enable bit
3
Serial I/O 1 interrupt enable bit q Serial I/O automatic transfer interrupt enable bit
q
0
4 Serial I/O 2 interrupt enable
bit Serial I/O 3 interrupt enable 5 bit 6 Timer 1 interrupt enable bit
7 Timer 2 interrupt enable bit
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
0 0 0 0
Fig. 3.3.28 Structure of Interrupt control register 1
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3. APPENDIX
3819 Group 3.3 Control registers
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control reigster 2 (ICON2) [Address:3F16]
b
Name
Function
0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset
RW
0 Timer 3 interrupt enable bit 1 Timer 4 interrupt enable bit 2 Timer 5 interrupt enable bit 3 Timer 6 interrupt enable bit 4 INT3 interrupt enable bit 5
q q
0 0 0 0 0 0
INT4 interrupt enable bit A-D conversion interrupt enable bit
6
FLD blanking interrupt enable bit q FLD digit interrupt enable bit
q
0 0
7 Fix this bit to "0."
Fig. 3.3.29 Structure of Interrupt control register 2
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3. APPENDIX
3.4 Mask ROM ordering method
3819 Group 3.4 Mask ROM ordering method
196
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3. APPENDIX
3819 Group 3.4 Mask ROM ordering method
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3. APPENDIX
3.5 Mark specification form
3819 Group 3.5 Mark specification form
198
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3. APPENDIX
3.6 Package outline
3819 Group 3.6 Package outline
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3. APPENDIX
3.7 Memory map
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P1 (P1) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) Port P9 (P9) Port PA (PA) Port PA direction register (PAD) Port PB (PB) Port PB direction register (PBD)
Serial I/O automatic transfer data pointer (SIODP)
3819 Group 3.7 Memory map
Serial I/O1 control register (SIO1CON)
Serial I/O automatic transfer control register (SIOAC)
Serial I/O1 register (SIO1)
Serial I/O automatic transfer interval register (SIOAI)
Serial I/O2 control register (SIO2CON) Serial I/O3 control register (SIO3CON) Serial I/O2 register (SIO2)
002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer 4 (T4) Timer 5 (T5) Timer 6 (T6) Serial I/O3 register (SIO3) Timer 6 PWM register (T6PWM) Timer 12 mode register (T12M) Timer 34 mode register (T34M) Timer 56 mode register (T56M) D-A conversion register (DA) AD-DA control register (ADCON) A-D conversion register (AD)
Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
Port P0 segment/digit switch register (P0SDR) Port P2 digit/port switch register (P2DPR) Port P8 segment/port switch register (P8SPR) Port PA segment/port switch register (PASPR) FLDC mode register 1 (FLDM1) FLDC mode register 2 (FLDM2) FLD data pointer (FLDDP) Zero cross detection control register (ZCRCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
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P87/SEG15 P86/SEG14 P85/SEG13 P84/SEG12 P83/SEG11 P82/SEG10 P81/SEG9 P80/SEG8 PA7/SEG7 PA6/SEG6 VCC PA5/SEG5 PA4/SEG4 PA3/SEG3 PA2/SEG2 PA1/SEG1 PA0/SEG0 VEE AVSS VREF
99
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
3.8 Pin configuration
M38197MA-XXXFP
Package type : 100P6S-A 100-pin plastic-molded QFP
3819 Group USER'S MANUAL
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 31
P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 PB3 PB2/DA P57/SRDY3/AN15 P56/SCLK3/AN14 P55/SOUT3/AN13 P54/SIN3/AN12 P53/SRDY2/AN11 P52/SCLK2/AN10 P51/SOUT2/AN9 P50/SIN2/AN8 P67/SRDY1/CS/SCLK12 P66/SCLK11 P65/SOUT1 P64/SIN1 P63/CNTR1 P62/CNTR0 P61/PWM P60 P47/T3OUT P46/T1OUT P45/INT1/ZCR P44/INT4
P90/SEG16 P91/SEG17 P92/SEG18 P93/SEG19 P94/SEG20 P95/SEG21 P96/SEG22 P97/SEG23 P30/SEG24 P31/SEG25 P32/SEG26 P33/SEG27 P34/SEG28 P35/SEG29 P36/SEG30 P37/SEG31 P00/SEG32/DIG0 P01/SEG33/DIG1 P02/SEG34/DIG2 P03/SEG35/DIG3 P04/SEG36/DIG4 P05/SEG37/DIG5 P06/SEG38/DIG6 P07/SEG39/DIG7 P10/SEG40/DIG8 P11/SEG41/DIG9 P12/DIG10 P13/DIG11 P14/DIG12 P15/DIG13
P16/DIG14 P17/DIG15 P20/DIG16 P21/DIG17 P22/DIG18 P23/DIG19 P24 P25 P26 P27 VSS XOUT XIN PB0/XCOUT PB1/XCIN RESET P40/INT0 P41 P42/INT2 P43/INT3
3819 Group 3.8 Pin configuration
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Mar. First Edition 1995 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
(c)1998 MITSUBISHI ELECTRIC CORPORATION
User's Manual 3819 Group
H-ED346-A KI-9503 Printed in Japan (ROD) (c) 1995 MITSUBISHI ELECTRIC CORPORATION.
New publication, effective Mar. 1995. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition Revision Description
3819 Group User's Manual
Rev. date 980216
(1/1)

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